O3CPU.py (10338:8bee5f4edb92) O3CPU.py (10785:f56c10663a01)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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27# Authors: Kevin Lim
28
29from m5.defines import buildEnv
30from m5.params import *
31from m5.proxy import *
32from BaseCPU import BaseCPU
33from FUPool import *
34from O3Checker import O3Checker
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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27# Authors: Kevin Lim
28
29from m5.defines import buildEnv
30from m5.params import *
31from m5.proxy import *
32from BaseCPU import BaseCPU
33from FUPool import *
34from O3Checker import O3Checker
35from BranchPredictor import BranchPredictor
35from BranchPredictor import *
36
37class DerivO3CPU(BaseCPU):
38 type = 'DerivO3CPU'
39 cxx_header = 'cpu/o3/deriv.hh'
40
41 @classmethod
42 def memory_mode(cls):
43 return 'timing'

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134 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
135 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
136 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
137 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
138 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
139 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
140 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
141
36
37class DerivO3CPU(BaseCPU):
38 type = 'DerivO3CPU'
39 cxx_header = 'cpu/o3/deriv.hh'
40
41 @classmethod
42 def memory_mode(cls):
43 return 'timing'

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134 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
135 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
136 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
137 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
138 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
139 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
140 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
141
142 branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
142 branchPred = Param.BranchPredictor(TournamentBP(numThreads =
143 Parent.numThreads),
144 "Branch Predictor")
145 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
146 "Enable TSO Memory model")
147
148 def addCheckerCpu(self):
149 if buildEnv['TARGET_ISA'] in ['arm']:
150 from ArmTLB import ArmTLB

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144 "Branch Predictor")
145 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
146 "Enable TSO Memory model")
147
148 def addCheckerCpu(self):
149 if buildEnv['TARGET_ISA'] in ['arm']:
150 from ArmTLB import ArmTLB

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