43,57c43,47
< if not buildEnv['FULL_SYSTEM']:
< # FIXME: Shouldn't need to derefernce Parent.workload
< # Somewhere in the param parsing code
< # src/python/m5/params.py is and error that
< # has trouble converting the workload parameter properly.
< checker = Param.BaseCPU(O3Checker(workload=Parent.workload[0],
< exitOnError=False,
< updateOnError=True,
< warnOnlyOnLoadError=True),
< "checker")
< else:
< checker = Param.BaseCPU(O3Checker(exitOnError=False,
< updateOnError=True,
< warnOnlyOnLoadError=True),
< "checker")
---
> checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
> exitOnError=False,
> updateOnError=True,
> warnOnlyOnLoadError=False),
> "checker")
61a52,54
> icache_port = Port("Instruction Port")
> dcache_port = Port("Data Port")
> _cached_ports = BaseCPU._cached_ports + ['icache_port', 'dcache_port']
152,153c145,148
< needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
< "Enable TSO Memory model")
---
> def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
> BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
> self.icache.tgts_per_mshr = 20
> self.dcache.tgts_per_mshr = 20