1# Copyright (c) 2016, 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from __future__ import print_function
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from BaseCPU import BaseCPU
47from FUPool import *
48from O3Checker import O3Checker
49from BranchPredictor import *
50
51class FetchPolicy(ScopedEnum):
52 vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
53
54class SMTQueuePolicy(ScopedEnum):
55 vals = [ 'Dynamic', 'Partitioned', 'Threshold' ]
56
57class CommitPolicy(ScopedEnum):
58 vals = [ 'Aggressive', 'RoundRobin', 'OldestReady' ]
59
60class DerivO3CPU(BaseCPU):
61 type = 'DerivO3CPU'
62 cxx_header = 'cpu/o3/deriv.hh'
63
64 @classmethod
65 def memory_mode(cls):
66 return 'timing'
67
68 @classmethod
69 def require_caches(cls):
70 return True
71
72 @classmethod
73 def support_take_over(cls):
74 return True
75
76 activity = Param.Unsigned(0, "Initial count")
77
78 cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
79 "Constrains stores only. Loads are constrained by load FUs.")
80
81 decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
82 renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
83 iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
84 "delay")
85 commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
86 fetchWidth = Param.Unsigned(8, "Fetch width")
87 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
88 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
89 "per-thread")
90
91 renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
92 iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
93 "delay")
94 commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
95 fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
96 decodeWidth = Param.Unsigned(8, "Decode width")
97
98 iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
99 "delay")
100 commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
101 decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
102 renameWidth = Param.Unsigned(8, "Rename width")
103
104 commitToIEWDelay = Param.Cycles(1, "Commit to "
105 "Issue/Execute/Writeback delay")
106 renameToIEWDelay = Param.Cycles(2, "Rename to "
107 "Issue/Execute/Writeback delay")
108 issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
109 "to the IEW stage)")
110 dispatchWidth = Param.Unsigned(8, "Dispatch width")
111 issueWidth = Param.Unsigned(8, "Issue width")
112 wbWidth = Param.Unsigned(8, "Writeback width")
113 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
114
115 iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
116 "delay")
117 renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
118 commitWidth = Param.Unsigned(8, "Commit width")
119 squashWidth = Param.Unsigned(8, "Squash width")
120 trapLatency = Param.Cycles(13, "Trap latency")
121 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
122
123 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
124 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
125
126 LQEntries = Param.Unsigned(32, "Number of load queue entries")
127 SQEntries = Param.Unsigned(32, "Number of store queue entries")
128 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
129 LSQCheckLoads = Param.Bool(True,
130 "Should dependency violations be checked for loads & stores or just stores")
131 store_set_clear_period = Param.Unsigned(250000,
132 "Number of load/store insts before the dep predictor should be invalidated")
133 LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
134 SSITSize = Param.Unsigned(1024, "Store set ID table size")
135
136 numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
137
138 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
139 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
140 "registers")
141 # most ISAs don't use condition-code regs, so default is 0
142 _defaultNumPhysCCRegs = 0
143 if buildEnv['TARGET_ISA'] in ('arm','x86'):
144 # For x86, each CC reg is used to hold only a subset of the
145 # flags, so we need 4-5 times the number of CC regs as
146 # physical integer regs to be sure we don't run out. In
147 # typical real machines, CC regs are not explicitly renamed
148 # (it's a side effect of int reg renaming), so they should
149 # never be the bottleneck here.
150 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
151 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
152 "registers")
| 1# Copyright (c) 2016, 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from __future__ import print_function
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from BaseCPU import BaseCPU
47from FUPool import *
48from O3Checker import O3Checker
49from BranchPredictor import *
50
51class FetchPolicy(ScopedEnum):
52 vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
53
54class SMTQueuePolicy(ScopedEnum):
55 vals = [ 'Dynamic', 'Partitioned', 'Threshold' ]
56
57class CommitPolicy(ScopedEnum):
58 vals = [ 'Aggressive', 'RoundRobin', 'OldestReady' ]
59
60class DerivO3CPU(BaseCPU):
61 type = 'DerivO3CPU'
62 cxx_header = 'cpu/o3/deriv.hh'
63
64 @classmethod
65 def memory_mode(cls):
66 return 'timing'
67
68 @classmethod
69 def require_caches(cls):
70 return True
71
72 @classmethod
73 def support_take_over(cls):
74 return True
75
76 activity = Param.Unsigned(0, "Initial count")
77
78 cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
79 "Constrains stores only. Loads are constrained by load FUs.")
80
81 decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
82 renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
83 iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
84 "delay")
85 commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
86 fetchWidth = Param.Unsigned(8, "Fetch width")
87 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
88 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
89 "per-thread")
90
91 renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
92 iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
93 "delay")
94 commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
95 fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
96 decodeWidth = Param.Unsigned(8, "Decode width")
97
98 iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
99 "delay")
100 commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
101 decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
102 renameWidth = Param.Unsigned(8, "Rename width")
103
104 commitToIEWDelay = Param.Cycles(1, "Commit to "
105 "Issue/Execute/Writeback delay")
106 renameToIEWDelay = Param.Cycles(2, "Rename to "
107 "Issue/Execute/Writeback delay")
108 issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
109 "to the IEW stage)")
110 dispatchWidth = Param.Unsigned(8, "Dispatch width")
111 issueWidth = Param.Unsigned(8, "Issue width")
112 wbWidth = Param.Unsigned(8, "Writeback width")
113 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
114
115 iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
116 "delay")
117 renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
118 commitWidth = Param.Unsigned(8, "Commit width")
119 squashWidth = Param.Unsigned(8, "Squash width")
120 trapLatency = Param.Cycles(13, "Trap latency")
121 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
122
123 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
124 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
125
126 LQEntries = Param.Unsigned(32, "Number of load queue entries")
127 SQEntries = Param.Unsigned(32, "Number of store queue entries")
128 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
129 LSQCheckLoads = Param.Bool(True,
130 "Should dependency violations be checked for loads & stores or just stores")
131 store_set_clear_period = Param.Unsigned(250000,
132 "Number of load/store insts before the dep predictor should be invalidated")
133 LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
134 SSITSize = Param.Unsigned(1024, "Store set ID table size")
135
136 numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
137
138 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
139 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
140 "registers")
141 # most ISAs don't use condition-code regs, so default is 0
142 _defaultNumPhysCCRegs = 0
143 if buildEnv['TARGET_ISA'] in ('arm','x86'):
144 # For x86, each CC reg is used to hold only a subset of the
145 # flags, so we need 4-5 times the number of CC regs as
146 # physical integer regs to be sure we don't run out. In
147 # typical real machines, CC regs are not explicitly renamed
148 # (it's a side effect of int reg renaming), so they should
149 # never be the bottleneck here.
150 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
151 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
152 "registers")
|
153 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
154 "Number of physical cc registers")
155 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
156 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
157
158 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
159 smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy")
160 smtLSQPolicy = Param.SMTQueuePolicy('Partitioned',
161 "SMT LSQ Sharing Policy")
162 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
163 smtIQPolicy = Param.SMTQueuePolicy('Partitioned',
164 "SMT IQ Sharing Policy")
165 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
166 smtROBPolicy = Param.SMTQueuePolicy('Partitioned',
167 "SMT ROB Sharing Policy")
168 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
169 smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy")
170
171 branchPred = Param.BranchPredictor(TournamentBP(numThreads =
172 Parent.numThreads),
173 "Branch Predictor")
174 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
175 "Enable TSO Memory model")
176
177 def addCheckerCpu(self):
178 if buildEnv['TARGET_ISA'] in ['arm']:
179 from ArmTLB import ArmTLB
180
181 self.checker = O3Checker(workload=self.workload,
182 exitOnError=False,
183 updateOnError=True,
184 warnOnlyOnLoadError=True)
185 self.checker.itb = ArmTLB(size = self.itb.size)
186 self.checker.dtb = ArmTLB(size = self.dtb.size)
187 self.checker.cpu_id = self.cpu_id
188
189 else:
190 print("ERROR: Checker only supported under ARM ISA!")
191 exit(1)
| 155 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
156 "Number of physical cc registers")
157 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
158 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
159
160 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
161 smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy")
162 smtLSQPolicy = Param.SMTQueuePolicy('Partitioned',
163 "SMT LSQ Sharing Policy")
164 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
165 smtIQPolicy = Param.SMTQueuePolicy('Partitioned',
166 "SMT IQ Sharing Policy")
167 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
168 smtROBPolicy = Param.SMTQueuePolicy('Partitioned',
169 "SMT ROB Sharing Policy")
170 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
171 smtCommitPolicy = Param.CommitPolicy('RoundRobin', "SMT Commit Policy")
172
173 branchPred = Param.BranchPredictor(TournamentBP(numThreads =
174 Parent.numThreads),
175 "Branch Predictor")
176 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
177 "Enable TSO Memory model")
178
179 def addCheckerCpu(self):
180 if buildEnv['TARGET_ISA'] in ['arm']:
181 from ArmTLB import ArmTLB
182
183 self.checker = O3Checker(workload=self.workload,
184 exitOnError=False,
185 updateOnError=True,
186 warnOnlyOnLoadError=True)
187 self.checker.itb = ArmTLB(size = self.itb.size)
188 self.checker.dtb = ArmTLB(size = self.dtb.size)
189 self.checker.cpu_id = self.cpu_id
190
191 else:
192 print("ERROR: Checker only supported under ARM ISA!")
193 exit(1)
|