1# Copyright (c) 2016, 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from __future__ import print_function
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from BaseCPU import BaseCPU
47from FUPool import *
48from O3Checker import O3Checker
49from BranchPredictor import *
50
51class FetchPolicy(ScopedEnum):
52 vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
53
54class SMTQueuePolicy(ScopedEnum):
55 vals = [ 'Dynamic', 'Partitioned', 'Threshold' ]
56
57class DerivO3CPU(BaseCPU):
58 type = 'DerivO3CPU'
59 cxx_header = 'cpu/o3/deriv.hh'
60
61 @classmethod
62 def memory_mode(cls):
63 return 'timing'
64
65 @classmethod
66 def require_caches(cls):
67 return True
68
69 @classmethod
70 def support_take_over(cls):
71 return True
72
73 activity = Param.Unsigned(0, "Initial count")
74
75 cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
76 "Constrains stores only. Loads are constrained by load FUs.")
77
78 decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
79 renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
80 iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
81 "delay")
82 commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
83 fetchWidth = Param.Unsigned(8, "Fetch width")
84 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
85 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
86 "per-thread")
87
88 renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
89 iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
90 "delay")
91 commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
92 fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
93 decodeWidth = Param.Unsigned(8, "Decode width")
94
95 iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
96 "delay")
97 commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
98 decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
99 renameWidth = Param.Unsigned(8, "Rename width")
100
101 commitToIEWDelay = Param.Cycles(1, "Commit to "
102 "Issue/Execute/Writeback delay")
103 renameToIEWDelay = Param.Cycles(2, "Rename to "
104 "Issue/Execute/Writeback delay")
105 issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
106 "to the IEW stage)")
107 dispatchWidth = Param.Unsigned(8, "Dispatch width")
108 issueWidth = Param.Unsigned(8, "Issue width")
109 wbWidth = Param.Unsigned(8, "Writeback width")
110 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
111
112 iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
113 "delay")
114 renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
115 commitWidth = Param.Unsigned(8, "Commit width")
116 squashWidth = Param.Unsigned(8, "Squash width")
117 trapLatency = Param.Cycles(13, "Trap latency")
118 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
119
120 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
121 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
122
123 LQEntries = Param.Unsigned(32, "Number of load queue entries")
124 SQEntries = Param.Unsigned(32, "Number of store queue entries")
125 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
126 LSQCheckLoads = Param.Bool(True,
127 "Should dependency violations be checked for loads & stores or just stores")
128 store_set_clear_period = Param.Unsigned(250000,
129 "Number of load/store insts before the dep predictor should be invalidated")
130 LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
131 SSITSize = Param.Unsigned(1024, "Store set ID table size")
132
133 numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
134
135 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
136 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
137 "registers")
138 # most ISAs don't use condition-code regs, so default is 0
139 _defaultNumPhysCCRegs = 0
140 if buildEnv['TARGET_ISA'] in ('arm','x86'):
141 # For x86, each CC reg is used to hold only a subset of the
142 # flags, so we need 4-5 times the number of CC regs as
143 # physical integer regs to be sure we don't run out. In
144 # typical real machines, CC regs are not explicitly renamed
145 # (it's a side effect of int reg renaming), so they should
146 # never be the bottleneck here.
147 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
148 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
149 "registers")
150 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
151 "Number of physical cc registers")
152 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
153 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
154
155 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
156 smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy")
157 smtLSQPolicy = Param.SMTQueuePolicy('Partitioned',
158 "SMT LSQ Sharing Policy")
159 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
160 smtIQPolicy = Param.SMTQueuePolicy('Partitioned',
161 "SMT IQ Sharing Policy")
162 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
| 1# Copyright (c) 2016, 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from __future__ import print_function
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from BaseCPU import BaseCPU
47from FUPool import *
48from O3Checker import O3Checker
49from BranchPredictor import *
50
51class FetchPolicy(ScopedEnum):
52 vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
53
54class SMTQueuePolicy(ScopedEnum):
55 vals = [ 'Dynamic', 'Partitioned', 'Threshold' ]
56
57class DerivO3CPU(BaseCPU):
58 type = 'DerivO3CPU'
59 cxx_header = 'cpu/o3/deriv.hh'
60
61 @classmethod
62 def memory_mode(cls):
63 return 'timing'
64
65 @classmethod
66 def require_caches(cls):
67 return True
68
69 @classmethod
70 def support_take_over(cls):
71 return True
72
73 activity = Param.Unsigned(0, "Initial count")
74
75 cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
76 "Constrains stores only. Loads are constrained by load FUs.")
77
78 decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
79 renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
80 iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
81 "delay")
82 commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
83 fetchWidth = Param.Unsigned(8, "Fetch width")
84 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
85 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
86 "per-thread")
87
88 renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
89 iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
90 "delay")
91 commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
92 fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
93 decodeWidth = Param.Unsigned(8, "Decode width")
94
95 iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
96 "delay")
97 commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
98 decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
99 renameWidth = Param.Unsigned(8, "Rename width")
100
101 commitToIEWDelay = Param.Cycles(1, "Commit to "
102 "Issue/Execute/Writeback delay")
103 renameToIEWDelay = Param.Cycles(2, "Rename to "
104 "Issue/Execute/Writeback delay")
105 issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
106 "to the IEW stage)")
107 dispatchWidth = Param.Unsigned(8, "Dispatch width")
108 issueWidth = Param.Unsigned(8, "Issue width")
109 wbWidth = Param.Unsigned(8, "Writeback width")
110 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
111
112 iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
113 "delay")
114 renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
115 commitWidth = Param.Unsigned(8, "Commit width")
116 squashWidth = Param.Unsigned(8, "Squash width")
117 trapLatency = Param.Cycles(13, "Trap latency")
118 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
119
120 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
121 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
122
123 LQEntries = Param.Unsigned(32, "Number of load queue entries")
124 SQEntries = Param.Unsigned(32, "Number of store queue entries")
125 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
126 LSQCheckLoads = Param.Bool(True,
127 "Should dependency violations be checked for loads & stores or just stores")
128 store_set_clear_period = Param.Unsigned(250000,
129 "Number of load/store insts before the dep predictor should be invalidated")
130 LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
131 SSITSize = Param.Unsigned(1024, "Store set ID table size")
132
133 numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
134
135 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
136 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
137 "registers")
138 # most ISAs don't use condition-code regs, so default is 0
139 _defaultNumPhysCCRegs = 0
140 if buildEnv['TARGET_ISA'] in ('arm','x86'):
141 # For x86, each CC reg is used to hold only a subset of the
142 # flags, so we need 4-5 times the number of CC regs as
143 # physical integer regs to be sure we don't run out. In
144 # typical real machines, CC regs are not explicitly renamed
145 # (it's a side effect of int reg renaming), so they should
146 # never be the bottleneck here.
147 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
148 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
149 "registers")
150 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
151 "Number of physical cc registers")
152 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
153 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
154
155 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
156 smtFetchPolicy = Param.FetchPolicy('SingleThread', "SMT Fetch policy")
157 smtLSQPolicy = Param.SMTQueuePolicy('Partitioned',
158 "SMT LSQ Sharing Policy")
159 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
160 smtIQPolicy = Param.SMTQueuePolicy('Partitioned',
161 "SMT IQ Sharing Policy")
162 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
|