1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.defines import buildEnv
30from m5.params import *
31from m5.proxy import *
32from BaseCPU import BaseCPU
33from FUPool import *
34from O3Checker import O3Checker
| 1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.defines import buildEnv
30from m5.params import *
31from m5.proxy import *
32from BaseCPU import BaseCPU
33from FUPool import *
34from O3Checker import O3Checker
|
36
37class DerivO3CPU(BaseCPU):
38 type = 'DerivO3CPU'
39 cxx_header = 'cpu/o3/deriv.hh'
40
41 @classmethod
42 def memory_mode(cls):
43 return 'timing'
44
45 @classmethod
46 def require_caches(cls):
47 return True
48
49 @classmethod
50 def support_take_over(cls):
51 return True
52
53 activity = Param.Unsigned(0, "Initial count")
54
55 cachePorts = Param.Unsigned(200, "Cache Ports")
56
57 decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
58 renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
59 iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
60 "delay")
61 commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
62 fetchWidth = Param.Unsigned(8, "Fetch width")
63 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
64 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
65 "per-thread")
66
67 renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
68 iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
69 "delay")
70 commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
71 fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
72 decodeWidth = Param.Unsigned(8, "Decode width")
73
74 iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
75 "delay")
76 commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
77 decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
78 renameWidth = Param.Unsigned(8, "Rename width")
79
80 commitToIEWDelay = Param.Cycles(1, "Commit to "
81 "Issue/Execute/Writeback delay")
82 renameToIEWDelay = Param.Cycles(2, "Rename to "
83 "Issue/Execute/Writeback delay")
84 issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
85 "to the IEW stage)")
86 dispatchWidth = Param.Unsigned(8, "Dispatch width")
87 issueWidth = Param.Unsigned(8, "Issue width")
88 wbWidth = Param.Unsigned(8, "Writeback width")
89 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
90
91 iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
92 "delay")
93 renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
94 commitWidth = Param.Unsigned(8, "Commit width")
95 squashWidth = Param.Unsigned(8, "Squash width")
96 trapLatency = Param.Cycles(13, "Trap latency")
97 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
98
99 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
100 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
101
102 LQEntries = Param.Unsigned(32, "Number of load queue entries")
103 SQEntries = Param.Unsigned(32, "Number of store queue entries")
104 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
105 LSQCheckLoads = Param.Bool(True,
106 "Should dependency violations be checked for loads & stores or just stores")
107 store_set_clear_period = Param.Unsigned(250000,
108 "Number of load/store insts before the dep predictor should be invalidated")
109 LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
110 SSITSize = Param.Unsigned(1024, "Store set ID table size")
111
112 numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
113
114 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
115 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
116 "registers")
117 # most ISAs don't use condition-code regs, so default is 0
118 _defaultNumPhysCCRegs = 0
119 if buildEnv['TARGET_ISA'] in ('arm','x86'):
120 # For x86, each CC reg is used to hold only a subset of the
121 # flags, so we need 4-5 times the number of CC regs as
122 # physical integer regs to be sure we don't run out. In
123 # typical real machines, CC regs are not explicitly renamed
124 # (it's a side effect of int reg renaming), so they should
125 # never be the bottleneck here.
126 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
127 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
128 "Number of physical cc registers")
129 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
130 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
131
132 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
133 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
134 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
135 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
136 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
137 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
138 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
139 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
140 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
141
| 36
37class DerivO3CPU(BaseCPU):
38 type = 'DerivO3CPU'
39 cxx_header = 'cpu/o3/deriv.hh'
40
41 @classmethod
42 def memory_mode(cls):
43 return 'timing'
44
45 @classmethod
46 def require_caches(cls):
47 return True
48
49 @classmethod
50 def support_take_over(cls):
51 return True
52
53 activity = Param.Unsigned(0, "Initial count")
54
55 cachePorts = Param.Unsigned(200, "Cache Ports")
56
57 decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
58 renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
59 iewToFetchDelay = Param.Cycles(1, "Issue/Execute/Writeback to fetch "
60 "delay")
61 commitToFetchDelay = Param.Cycles(1, "Commit to fetch delay")
62 fetchWidth = Param.Unsigned(8, "Fetch width")
63 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
64 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
65 "per-thread")
66
67 renameToDecodeDelay = Param.Cycles(1, "Rename to decode delay")
68 iewToDecodeDelay = Param.Cycles(1, "Issue/Execute/Writeback to decode "
69 "delay")
70 commitToDecodeDelay = Param.Cycles(1, "Commit to decode delay")
71 fetchToDecodeDelay = Param.Cycles(1, "Fetch to decode delay")
72 decodeWidth = Param.Unsigned(8, "Decode width")
73
74 iewToRenameDelay = Param.Cycles(1, "Issue/Execute/Writeback to rename "
75 "delay")
76 commitToRenameDelay = Param.Cycles(1, "Commit to rename delay")
77 decodeToRenameDelay = Param.Cycles(1, "Decode to rename delay")
78 renameWidth = Param.Unsigned(8, "Rename width")
79
80 commitToIEWDelay = Param.Cycles(1, "Commit to "
81 "Issue/Execute/Writeback delay")
82 renameToIEWDelay = Param.Cycles(2, "Rename to "
83 "Issue/Execute/Writeback delay")
84 issueToExecuteDelay = Param.Cycles(1, "Issue to execute delay (internal "
85 "to the IEW stage)")
86 dispatchWidth = Param.Unsigned(8, "Dispatch width")
87 issueWidth = Param.Unsigned(8, "Issue width")
88 wbWidth = Param.Unsigned(8, "Writeback width")
89 fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
90
91 iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
92 "delay")
93 renameToROBDelay = Param.Cycles(1, "Rename to reorder buffer delay")
94 commitWidth = Param.Unsigned(8, "Commit width")
95 squashWidth = Param.Unsigned(8, "Squash width")
96 trapLatency = Param.Cycles(13, "Trap latency")
97 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
98
99 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
100 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
101
102 LQEntries = Param.Unsigned(32, "Number of load queue entries")
103 SQEntries = Param.Unsigned(32, "Number of store queue entries")
104 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
105 LSQCheckLoads = Param.Bool(True,
106 "Should dependency violations be checked for loads & stores or just stores")
107 store_set_clear_period = Param.Unsigned(250000,
108 "Number of load/store insts before the dep predictor should be invalidated")
109 LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
110 SSITSize = Param.Unsigned(1024, "Store set ID table size")
111
112 numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
113
114 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
115 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
116 "registers")
117 # most ISAs don't use condition-code regs, so default is 0
118 _defaultNumPhysCCRegs = 0
119 if buildEnv['TARGET_ISA'] in ('arm','x86'):
120 # For x86, each CC reg is used to hold only a subset of the
121 # flags, so we need 4-5 times the number of CC regs as
122 # physical integer regs to be sure we don't run out. In
123 # typical real machines, CC regs are not explicitly renamed
124 # (it's a side effect of int reg renaming), so they should
125 # never be the bottleneck here.
126 _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
127 numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
128 "Number of physical cc registers")
129 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
130 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
131
132 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
133 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
134 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
135 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
136 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
137 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
138 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
139 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
140 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
141
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