FuncUnitConfig.py (7760:e93e7e0caae1) FuncUnitConfig.py (10806:b9410e821c41)
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from m5.SimObject import SimObject
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from m5.SimObject import SimObject
42from m5.defines import buildEnv
42from m5.params import *
43from FuncUnit import *
44
45class IntALU(FUDesc):
46 opList = [ OpDesc(opClass='IntAlu') ]
47 count = 6
48
49class IntMultDiv(FUDesc):
50 opList = [ OpDesc(opClass='IntMult', opLat=3),
51 OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
43from m5.params import *
44from FuncUnit import *
45
46class IntALU(FUDesc):
47 opList = [ OpDesc(opClass='IntAlu') ]
48 count = 6
49
50class IntMultDiv(FUDesc):
51 opList = [ OpDesc(opClass='IntMult', opLat=3),
52 OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
53
54 # DIV and IDIV instructions in x86 are implemented using a loop which
55 # issues division microops. The latency of these microops should really be
56 # one (or a small number) cycle each since each of these computes one bit
57 # of the quotient.
58 if buildEnv['TARGET_ISA'] in ('x86'):
59 opList[1].opLat=1
60 opList[1].issueLat=1
61
52 count=2
53
54class FP_ALU(FUDesc):
55 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
56 OpDesc(opClass='FloatCmp', opLat=2),
57 OpDesc(opClass='FloatCvt', opLat=2) ]
58 count = 4
59

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63
64class FP_ALU(FUDesc):
65 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
66 OpDesc(opClass='FloatCmp', opLat=2),
67 OpDesc(opClass='FloatCvt', opLat=2) ]
68 count = 4
69

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