FuncUnitConfig.py (10806:b9410e821c41) FuncUnitConfig.py (10807:dac26eb4cb64)
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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44from FuncUnit import *
45
46class IntALU(FUDesc):
47 opList = [ OpDesc(opClass='IntAlu') ]
48 count = 6
49
50class IntMultDiv(FUDesc):
51 opList = [ OpDesc(opClass='IntMult', opLat=3),
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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44from FuncUnit import *
45
46class IntALU(FUDesc):
47 opList = [ OpDesc(opClass='IntAlu') ]
48 count = 6
49
50class IntMultDiv(FUDesc):
51 opList = [ OpDesc(opClass='IntMult', opLat=3),
52 OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
52 OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
53
54 # DIV and IDIV instructions in x86 are implemented using a loop which
55 # issues division microops. The latency of these microops should really be
56 # one (or a small number) cycle each since each of these computes one bit
57 # of the quotient.
58 if buildEnv['TARGET_ISA'] in ('x86'):
59 opList[1].opLat=1
53
54 # DIV and IDIV instructions in x86 are implemented using a loop which
55 # issues division microops. The latency of these microops should really be
56 # one (or a small number) cycle each since each of these computes one bit
57 # of the quotient.
58 if buildEnv['TARGET_ISA'] in ('x86'):
59 opList[1].opLat=1
60 opList[1].issueLat=1
61
62 count=2
63
64class FP_ALU(FUDesc):
65 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
66 OpDesc(opClass='FloatCmp', opLat=2),
67 OpDesc(opClass='FloatCvt', opLat=2) ]
68 count = 4
69
70class FP_MultDiv(FUDesc):
71 opList = [ OpDesc(opClass='FloatMult', opLat=4),
60
61 count=2
62
63class FP_ALU(FUDesc):
64 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
65 OpDesc(opClass='FloatCmp', opLat=2),
66 OpDesc(opClass='FloatCvt', opLat=2) ]
67 count = 4
68
69class FP_MultDiv(FUDesc):
70 opList = [ OpDesc(opClass='FloatMult', opLat=4),
72 OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
73 OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
71 OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
72 OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ]
74 count = 2
75
76class SIMD_Unit(FUDesc):
77 opList = [ OpDesc(opClass='SimdAdd'),
78 OpDesc(opClass='SimdAddAcc'),
79 OpDesc(opClass='SimdAlu'),
80 OpDesc(opClass='SimdCmp'),
81 OpDesc(opClass='SimdCvt'),

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104 opList = [ OpDesc(opClass='MemWrite') ]
105 count = 0
106
107class RdWrPort(FUDesc):
108 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
109 count = 4
110
111class IprPort(FUDesc):
73 count = 2
74
75class SIMD_Unit(FUDesc):
76 opList = [ OpDesc(opClass='SimdAdd'),
77 OpDesc(opClass='SimdAddAcc'),
78 OpDesc(opClass='SimdAlu'),
79 OpDesc(opClass='SimdCmp'),
80 OpDesc(opClass='SimdCvt'),

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103 opList = [ OpDesc(opClass='MemWrite') ]
104 count = 0
105
106class RdWrPort(FUDesc):
107 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
108 count = 4
109
110class IprPort(FUDesc):
112 opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
111 opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ]
113 count = 1
114
112 count = 1
113