1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Kevin Lim 40 41from m5.SimObject import SimObject 42from m5.defines import buildEnv 43from m5.params import * 44from FuncUnit import * 45 46class IntALU(FUDesc): 47 opList = [ OpDesc(opClass='IntAlu') ] 48 count = 6 49 50class IntMultDiv(FUDesc): 51 opList = [ OpDesc(opClass='IntMult', opLat=3), 52 OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ] 53 54 # DIV and IDIV instructions in x86 are implemented using a loop which 55 # issues division microops. The latency of these microops should really be 56 # one (or a small number) cycle each since each of these computes one bit 57 # of the quotient. 58 if buildEnv['TARGET_ISA'] in ('x86'): 59 opList[1].opLat=1 60 61 count=2 62 63class FP_ALU(FUDesc): 64 opList = [ OpDesc(opClass='FloatAdd', opLat=2), 65 OpDesc(opClass='FloatCmp', opLat=2), 66 OpDesc(opClass='FloatCvt', opLat=2) ] 67 count = 4 68 69class FP_MultDiv(FUDesc): 70 opList = [ OpDesc(opClass='FloatMult', opLat=4),
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71 OpDesc(opClass='FloatMultAcc', opLat=5), 72 OpDesc(opClass='FloatMisc', opLat=3), |
73 OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), 74 OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ] 75 count = 2 76 77class SIMD_Unit(FUDesc): 78 opList = [ OpDesc(opClass='SimdAdd'), 79 OpDesc(opClass='SimdAddAcc'), 80 OpDesc(opClass='SimdAlu'), 81 OpDesc(opClass='SimdCmp'), 82 OpDesc(opClass='SimdCvt'), 83 OpDesc(opClass='SimdMisc'), 84 OpDesc(opClass='SimdMult'), 85 OpDesc(opClass='SimdMultAcc'), 86 OpDesc(opClass='SimdShift'), 87 OpDesc(opClass='SimdShiftAcc'), 88 OpDesc(opClass='SimdSqrt'), 89 OpDesc(opClass='SimdFloatAdd'), 90 OpDesc(opClass='SimdFloatAlu'), 91 OpDesc(opClass='SimdFloatCmp'), 92 OpDesc(opClass='SimdFloatCvt'), 93 OpDesc(opClass='SimdFloatDiv'), 94 OpDesc(opClass='SimdFloatMisc'), 95 OpDesc(opClass='SimdFloatMult'), 96 OpDesc(opClass='SimdFloatMultAcc'), 97 OpDesc(opClass='SimdFloatSqrt') ] 98 count = 4 99 100class ReadPort(FUDesc):
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99 opList = [ OpDesc(opClass='MemRead') ]
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101 opList = [ OpDesc(opClass='MemRead'), 102 OpDesc(opClass='FloatMemRead') ] |
103 count = 0 104 105class WritePort(FUDesc):
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103 opList = [ OpDesc(opClass='MemWrite') ]
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106 opList = [ OpDesc(opClass='MemWrite'), 107 OpDesc(opClass='FloatMemWrite') ] |
108 count = 0 109 110class RdWrPort(FUDesc):
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107 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
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111 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'), 112 OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')] |
113 count = 4 114 115class IprPort(FUDesc): 116 opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ] 117 count = 1 118
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