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> from m5.defines import buildEnv
51a53,61
>
> # DIV and IDIV instructions in x86 are implemented using a loop which
> # issues division microops. The latency of these microops should really be
> # one (or a small number) cycle each since each of these computes one bit
> # of the quotient.
> if buildEnv['TARGET_ISA'] in ('x86'):
> opList[1].opLat=1
> opList[1].issueLat=1
>