1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from m5.SimObject import SimObject
| 1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from m5.SimObject import SimObject
|
| 42from m5.defines import buildEnv
|
42from m5.params import *
43from FuncUnit import *
44
45class IntALU(FUDesc):
46 opList = [ OpDesc(opClass='IntAlu') ]
47 count = 6
48
49class IntMultDiv(FUDesc):
50 opList = [ OpDesc(opClass='IntMult', opLat=3),
51 OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
| 43from m5.params import *
44from FuncUnit import *
45
46class IntALU(FUDesc):
47 opList = [ OpDesc(opClass='IntAlu') ]
48 count = 6
49
50class IntMultDiv(FUDesc):
51 opList = [ OpDesc(opClass='IntMult', opLat=3),
52 OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
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| 53
54 # DIV and IDIV instructions in x86 are implemented using a loop which
55 # issues division microops. The latency of these microops should really be
56 # one (or a small number) cycle each since each of these computes one bit
57 # of the quotient.
58 if buildEnv['TARGET_ISA'] in ('x86'):
59 opList[1].opLat=1
60 opList[1].issueLat=1
61
|
52 count=2
53
54class FP_ALU(FUDesc):
55 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
56 OpDesc(opClass='FloatCmp', opLat=2),
57 OpDesc(opClass='FloatCvt', opLat=2) ]
58 count = 4
59
60class FP_MultDiv(FUDesc):
61 opList = [ OpDesc(opClass='FloatMult', opLat=4),
62 OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
63 OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
64 count = 2
65
66class SIMD_Unit(FUDesc):
67 opList = [ OpDesc(opClass='SimdAdd'),
68 OpDesc(opClass='SimdAddAcc'),
69 OpDesc(opClass='SimdAlu'),
70 OpDesc(opClass='SimdCmp'),
71 OpDesc(opClass='SimdCvt'),
72 OpDesc(opClass='SimdMisc'),
73 OpDesc(opClass='SimdMult'),
74 OpDesc(opClass='SimdMultAcc'),
75 OpDesc(opClass='SimdShift'),
76 OpDesc(opClass='SimdShiftAcc'),
77 OpDesc(opClass='SimdSqrt'),
78 OpDesc(opClass='SimdFloatAdd'),
79 OpDesc(opClass='SimdFloatAlu'),
80 OpDesc(opClass='SimdFloatCmp'),
81 OpDesc(opClass='SimdFloatCvt'),
82 OpDesc(opClass='SimdFloatDiv'),
83 OpDesc(opClass='SimdFloatMisc'),
84 OpDesc(opClass='SimdFloatMult'),
85 OpDesc(opClass='SimdFloatMultAcc'),
86 OpDesc(opClass='SimdFloatSqrt') ]
87 count = 4
88
89class ReadPort(FUDesc):
90 opList = [ OpDesc(opClass='MemRead') ]
91 count = 0
92
93class WritePort(FUDesc):
94 opList = [ OpDesc(opClass='MemWrite') ]
95 count = 0
96
97class RdWrPort(FUDesc):
98 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
99 count = 4
100
101class IprPort(FUDesc):
102 opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
103 count = 1
104
| 62 count=2
63
64class FP_ALU(FUDesc):
65 opList = [ OpDesc(opClass='FloatAdd', opLat=2),
66 OpDesc(opClass='FloatCmp', opLat=2),
67 OpDesc(opClass='FloatCvt', opLat=2) ]
68 count = 4
69
70class FP_MultDiv(FUDesc):
71 opList = [ OpDesc(opClass='FloatMult', opLat=4),
72 OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
73 OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
74 count = 2
75
76class SIMD_Unit(FUDesc):
77 opList = [ OpDesc(opClass='SimdAdd'),
78 OpDesc(opClass='SimdAddAcc'),
79 OpDesc(opClass='SimdAlu'),
80 OpDesc(opClass='SimdCmp'),
81 OpDesc(opClass='SimdCvt'),
82 OpDesc(opClass='SimdMisc'),
83 OpDesc(opClass='SimdMult'),
84 OpDesc(opClass='SimdMultAcc'),
85 OpDesc(opClass='SimdShift'),
86 OpDesc(opClass='SimdShiftAcc'),
87 OpDesc(opClass='SimdSqrt'),
88 OpDesc(opClass='SimdFloatAdd'),
89 OpDesc(opClass='SimdFloatAlu'),
90 OpDesc(opClass='SimdFloatCmp'),
91 OpDesc(opClass='SimdFloatCvt'),
92 OpDesc(opClass='SimdFloatDiv'),
93 OpDesc(opClass='SimdFloatMisc'),
94 OpDesc(opClass='SimdFloatMult'),
95 OpDesc(opClass='SimdFloatMultAcc'),
96 OpDesc(opClass='SimdFloatSqrt') ]
97 count = 4
98
99class ReadPort(FUDesc):
100 opList = [ OpDesc(opClass='MemRead') ]
101 count = 0
102
103class WritePort(FUDesc):
104 opList = [ OpDesc(opClass='MemWrite') ]
105 count = 0
106
107class RdWrPort(FUDesc):
108 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
109 count = 4
110
111class IprPort(FUDesc):
112 opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
113 count = 1
114
|