FuncUnitConfig.py (10807:dac26eb4cb64) | FuncUnitConfig.py (11683:f1e198a028be) |
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1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 54 unchanged lines hidden (view full) --- 63class FP_ALU(FUDesc): 64 opList = [ OpDesc(opClass='FloatAdd', opLat=2), 65 OpDesc(opClass='FloatCmp', opLat=2), 66 OpDesc(opClass='FloatCvt', opLat=2) ] 67 count = 4 68 69class FP_MultDiv(FUDesc): 70 opList = [ OpDesc(opClass='FloatMult', opLat=4), | 1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 54 unchanged lines hidden (view full) --- 63class FP_ALU(FUDesc): 64 opList = [ OpDesc(opClass='FloatAdd', opLat=2), 65 OpDesc(opClass='FloatCmp', opLat=2), 66 OpDesc(opClass='FloatCvt', opLat=2) ] 67 count = 4 68 69class FP_MultDiv(FUDesc): 70 opList = [ OpDesc(opClass='FloatMult', opLat=4), |
71 OpDesc(opClass='FloatMultAcc', opLat=5), 72 OpDesc(opClass='FloatMisc', opLat=3), |
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71 OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), 72 OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ] 73 count = 2 74 75class SIMD_Unit(FUDesc): 76 opList = [ OpDesc(opClass='SimdAdd'), 77 OpDesc(opClass='SimdAddAcc'), 78 OpDesc(opClass='SimdAlu'), --- 12 unchanged lines hidden (view full) --- 91 OpDesc(opClass='SimdFloatDiv'), 92 OpDesc(opClass='SimdFloatMisc'), 93 OpDesc(opClass='SimdFloatMult'), 94 OpDesc(opClass='SimdFloatMultAcc'), 95 OpDesc(opClass='SimdFloatSqrt') ] 96 count = 4 97 98class ReadPort(FUDesc): | 73 OpDesc(opClass='FloatDiv', opLat=12, pipelined=False), 74 OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ] 75 count = 2 76 77class SIMD_Unit(FUDesc): 78 opList = [ OpDesc(opClass='SimdAdd'), 79 OpDesc(opClass='SimdAddAcc'), 80 OpDesc(opClass='SimdAlu'), --- 12 unchanged lines hidden (view full) --- 93 OpDesc(opClass='SimdFloatDiv'), 94 OpDesc(opClass='SimdFloatMisc'), 95 OpDesc(opClass='SimdFloatMult'), 96 OpDesc(opClass='SimdFloatMultAcc'), 97 OpDesc(opClass='SimdFloatSqrt') ] 98 count = 4 99 100class ReadPort(FUDesc): |
99 opList = [ OpDesc(opClass='MemRead') ] | 101 opList = [ OpDesc(opClass='MemRead'), 102 OpDesc(opClass='FloatMemRead') ] |
100 count = 0 101 102class WritePort(FUDesc): | 103 count = 0 104 105class WritePort(FUDesc): |
103 opList = [ OpDesc(opClass='MemWrite') ] | 106 opList = [ OpDesc(opClass='MemWrite'), 107 OpDesc(opClass='FloatMemWrite') ] |
104 count = 0 105 106class RdWrPort(FUDesc): | 108 count = 0 109 110class RdWrPort(FUDesc): |
107 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ] | 111 opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'), 112 OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')] |
108 count = 4 109 110class IprPort(FUDesc): 111 opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ] 112 count = 1 113 | 113 count = 4 114 115class IprPort(FUDesc): 116 opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ] 117 count = 1 118 |