nativetrace.hh (5038:c996bb7f1a6d) nativetrace.hh (5049:16a0724434b8)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32#ifndef __NATIVETRACE_HH__
33#define __NATIVETRACE_HH__
34
35#include "base/trace.hh"
36#include "cpu/static_inst.hh"
37#include "sim/host.hh"
38#include "sim/insttracer.hh"
39#include "arch/x86/intregs.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32#ifndef __NATIVETRACE_HH__
33#define __NATIVETRACE_HH__
34
35#include "base/trace.hh"
36#include "cpu/static_inst.hh"
37#include "sim/host.hh"
38#include "sim/insttracer.hh"
39#include "arch/x86/intregs.hh"
40#include "arch/x86/floatregs.hh"
40
41class ThreadContext;
42
43
44namespace Trace {
45
46class NativeTrace;
47

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86 uint64_t r9;
87 uint64_t r10;
88 uint64_t r11;
89 uint64_t r12;
90 uint64_t r13;
91 uint64_t r14;
92 uint64_t r15;
93 uint64_t rip;
41
42class ThreadContext;
43
44
45namespace Trace {
46
47class NativeTrace;
48

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87 uint64_t r9;
88 uint64_t r10;
89 uint64_t r11;
90 uint64_t r12;
91 uint64_t r13;
92 uint64_t r14;
93 uint64_t r15;
94 uint64_t rip;
95 //This should be expanded to 16 if x87 registers are considered
96 uint64_t mmx[8];
97 uint64_t xmm[32];
94
95 void update(int fd)
96 {
97 int bytesLeft = sizeof(ThreadState);
98 int bytesRead = 0;
99 do
100 {
101 int res = read(fd, ((char *)this) + bytesRead, bytesLeft);

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116 r9 = TheISA::gtoh(r9);
117 r10 = TheISA::gtoh(r10);
118 r11 = TheISA::gtoh(r11);
119 r12 = TheISA::gtoh(r12);
120 r13 = TheISA::gtoh(r13);
121 r14 = TheISA::gtoh(r14);
122 r15 = TheISA::gtoh(r15);
123 rip = TheISA::gtoh(rip);
98
99 void update(int fd)
100 {
101 int bytesLeft = sizeof(ThreadState);
102 int bytesRead = 0;
103 do
104 {
105 int res = read(fd, ((char *)this) + bytesRead, bytesLeft);

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120 r9 = TheISA::gtoh(r9);
121 r10 = TheISA::gtoh(r10);
122 r11 = TheISA::gtoh(r11);
123 r12 = TheISA::gtoh(r12);
124 r13 = TheISA::gtoh(r13);
125 r14 = TheISA::gtoh(r14);
126 r15 = TheISA::gtoh(r15);
127 rip = TheISA::gtoh(rip);
128 //This should be expanded if x87 registers are considered
129 for (int i = 0; i < 8; i++)
130 mmx[i] = TheISA::gtoh(mmx[i]);
131 for (int i = 0; i < 32; i++)
132 xmm[i] = TheISA::gtoh(xmm[i]);
124 }
125
126 void update(ThreadContext * tc)
127 {
128 rax = tc->readIntReg(X86ISA::INTREG_RAX);
129 rcx = tc->readIntReg(X86ISA::INTREG_RCX);
130 rdx = tc->readIntReg(X86ISA::INTREG_RDX);
131 rbx = tc->readIntReg(X86ISA::INTREG_RBX);

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137 r9 = tc->readIntReg(X86ISA::INTREG_R9);
138 r10 = tc->readIntReg(X86ISA::INTREG_R10);
139 r11 = tc->readIntReg(X86ISA::INTREG_R11);
140 r12 = tc->readIntReg(X86ISA::INTREG_R12);
141 r13 = tc->readIntReg(X86ISA::INTREG_R13);
142 r14 = tc->readIntReg(X86ISA::INTREG_R14);
143 r15 = tc->readIntReg(X86ISA::INTREG_R15);
144 rip = tc->readNextPC();
133 }
134
135 void update(ThreadContext * tc)
136 {
137 rax = tc->readIntReg(X86ISA::INTREG_RAX);
138 rcx = tc->readIntReg(X86ISA::INTREG_RCX);
139 rdx = tc->readIntReg(X86ISA::INTREG_RDX);
140 rbx = tc->readIntReg(X86ISA::INTREG_RBX);

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146 r9 = tc->readIntReg(X86ISA::INTREG_R9);
147 r10 = tc->readIntReg(X86ISA::INTREG_R10);
148 r11 = tc->readIntReg(X86ISA::INTREG_R11);
149 r12 = tc->readIntReg(X86ISA::INTREG_R12);
150 r13 = tc->readIntReg(X86ISA::INTREG_R13);
151 r14 = tc->readIntReg(X86ISA::INTREG_R14);
152 r15 = tc->readIntReg(X86ISA::INTREG_R15);
153 rip = tc->readNextPC();
154 //This should be expanded if x87 registers are considered
155 for (int i = 0; i < 8; i++)
156 mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
157 for (int i = 0; i < 32; i++)
158 xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
145 }
146
147 };
148
149 ThreadState nState;
150 ThreadState mState;
151
152

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166 }
167
168 bool
169 checkRcxReg(const char * regName, uint64_t &, uint64_t &);
170
171 bool
172 checkR11Reg(const char * regName, uint64_t &, uint64_t &);
173
159 }
160
161 };
162
163 ThreadState nState;
164 ThreadState mState;
165
166

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180 }
181
182 bool
183 checkRcxReg(const char * regName, uint64_t &, uint64_t &);
184
185 bool
186 checkR11Reg(const char * regName, uint64_t &, uint64_t &);
187
188 bool
189 checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
190
174 NativeTrace(const Params *p);
175
176 NativeTraceRecord *
177 getInstRecord(Tick when, ThreadContext *tc,
178 const StaticInstPtr staticInst, Addr pc)
179 {
180 if (tc->misspeculating())
181 return NULL;

--- 14 unchanged lines hidden --- 		191 NativeTrace(const Params *p);
192
193 NativeTraceRecord *
194 getInstRecord(Tick when, ThreadContext *tc,
195 const StaticInstPtr staticInst, Addr pc)
196 {
197 if (tc->misspeculating())
198 return NULL;

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