scoreboard.cc (12104:edd63f9c6184) scoreboard.cc (12106:7784fac1b159)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include "cpu/reg_class.hh"
44#include "debug/MinorScoreboard.hh"
45#include "debug/MinorTiming.hh"
46
47namespace Minor
48{
49
50bool
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include "cpu/reg_class.hh"
44#include "debug/MinorScoreboard.hh"
45#include "debug/MinorTiming.hh"
46
47namespace Minor
48{
49
50bool
51Scoreboard::findIndex(RegId reg, Index &scoreboard_index)
51Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index)
52{
53 bool ret = false;
54
55 if (reg.isZeroReg()) {
56 /* Don't bother with the zero register */
57 ret = false;
58 } else {
52{
53 bool ret = false;
54
55 if (reg.isZeroReg()) {
56 /* Don't bother with the zero register */
57 ret = false;
58 } else {
59 switch (reg.regClass)
59 switch (reg.classValue())
60 {
61 case IntRegClass:
60 {
61 case IntRegClass:
62 scoreboard_index = reg.regIdx;
62 scoreboard_index = reg.index();
63 ret = true;
64 break;
65 case FloatRegClass:
66 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
63 ret = true;
64 break;
65 case FloatRegClass:
66 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
67 reg.regIdx;
67 reg.index();
68 ret = true;
69 break;
70 case CCRegClass:
68 ret = true;
69 break;
70 case CCRegClass:
71 scoreboard_index = TheISA::NumIntRegs + reg.regIdx;
71 scoreboard_index = TheISA::NumIntRegs + reg.index();
72 ret = true;
73 break;
74 case MiscRegClass:
75 /* Don't bother with Misc registers */
76 ret = false;
77 break;
78 }
79 }
80
81 return ret;
82}
83
84/** Flatten a RegId, irrespective of what reg type it's pointing to */
85static RegId
72 ret = true;
73 break;
74 case MiscRegClass:
75 /* Don't bother with Misc registers */
76 ret = false;
77 break;
78 }
79 }
80
81 return ret;
82}
83
84/** Flatten a RegId, irrespective of what reg type it's pointing to */
85static RegId
86flattenRegIndex(RegId reg, ThreadContext *thread_context)
86flattenRegIndex(const RegId& reg, ThreadContext *thread_context)
87{
87{
88 switch (reg.regClass)
89 {
90 case IntRegClass:
91 reg.regIdx = thread_context->flattenIntIndex(reg.regIdx);
92 break;
93 case FloatRegClass:
94 reg.regIdx = thread_context->flattenFloatIndex(reg.regIdx);
95 break;
96 case CCRegClass:
97 reg.regIdx = thread_context->flattenCCIndex(reg.regIdx);
98 break;
99 case MiscRegClass:
100 /* Don't bother to flatten misc regs as we don't need them here */
101 /* return thread_context->flattenMiscIndex(reg); */
102 break;
103 }
104
105 return reg;
88 return thread_context->flattenRegId(reg);
106}
107
108void
109Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
110 ThreadContext *thread_context, bool mark_unpredictable)
111{
112 if (inst->isFault())
113 return;

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138 fuIndices[index] = inst->fuIndex;
139 }
140
141 DPRINTF(MinorScoreboard, "Marking up inst: %s"
142 " regIndex: %d final numResults: %d returnCycle: %d\n",
143 *inst, index, numResults[index], returnCycle[index]);
144 } else {
145 /* Use ZeroReg to mark invalid/untracked dests */
89}
90
91void
92Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
93 ThreadContext *thread_context, bool mark_unpredictable)
94{
95 if (inst->isFault())
96 return;

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121 fuIndices[index] = inst->fuIndex;
122 }
123
124 DPRINTF(MinorScoreboard, "Marking up inst: %s"
125 " regIndex: %d final numResults: %d returnCycle: %d\n",
126 *inst, index, numResults[index], returnCycle[index]);
127 } else {
128 /* Use ZeroReg to mark invalid/untracked dests */
146 inst->flatDestRegIdx[dest_index] = RegId::zeroReg;
129 inst->flatDestRegIdx[dest_index] = RegId(IntRegClass,
130 TheISA::ZeroReg);
147 }
148 }
149}
150
151InstSeqNum
152Scoreboard::execSeqNumToWaitFor(MinorDynInstPtr inst,
153 ThreadContext *thread_context)
154{

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185
186 StaticInstPtr staticInst = inst->staticInst;
187 unsigned int num_dests = staticInst->numDestRegs();
188
189 /** Mark each destination register */
190 for (unsigned int dest_index = 0; dest_index < num_dests;
191 dest_index++)
192 {
131 }
132 }
133}
134
135InstSeqNum
136Scoreboard::execSeqNumToWaitFor(MinorDynInstPtr inst,
137 ThreadContext *thread_context)
138{

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169
170 StaticInstPtr staticInst = inst->staticInst;
171 unsigned int num_dests = staticInst->numDestRegs();
172
173 /** Mark each destination register */
174 for (unsigned int dest_index = 0; dest_index < num_dests;
175 dest_index++)
176 {
193 RegId reg = inst->flatDestRegIdx[dest_index];
177 const RegId& reg = inst->flatDestRegIdx[dest_index];
194 Index index;
195
196 if (findIndex(reg, index)) {
197 if (clear_unpredictable && numUnpredictableResults[index] != 0)
198 numUnpredictableResults[index] --;
199
200 numResults[index] --;
201

--- 118 unchanged lines hidden --- 		178 Index index;
179
180 if (findIndex(reg, index)) {
181 if (clear_unpredictable && numUnpredictableResults[index] != 0)
182 numUnpredictableResults[index] --;
183
184 numResults[index] --;
185

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