pipeline.hh (12284:b91c036913da) | pipeline.hh (12324:6142a2fec8d9) |
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1/* 2 * Copyright (c) 2013-2014, 2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 114 unchanged lines hidden (view full) --- 123 bool isDrained(); 124 125 /** A custom evaluate allows report in the right place (between 126 * stages and pipeline advance) */ 127 void evaluate() override; 128 129 void minorTrace() const; 130 | 1/* 2 * Copyright (c) 2013-2014, 2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 114 unchanged lines hidden (view full) --- 123 bool isDrained(); 124 125 /** A custom evaluate allows report in the right place (between 126 * stages and pipeline advance) */ 127 void evaluate() override; 128 129 void minorTrace() const; 130 |
131 /** Stats registering */ 132 void regStats(); 133 |
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131 /** Functions below here are BaseCPU operations passed on to pipeline 132 * stages */ 133 134 /** Return the IcachePort belonging to Fetch1 for the CPU */ 135 MinorCPU::MinorCPUPort &getInstPort(); 136 /** Return the DcachePort belonging to Execute for the CPU */ 137 MinorCPU::MinorCPUPort &getDataPort(); 138 139 /** To give the activity recorder to the CPU */ 140 MinorActivityRecorder *getActivityRecorder() { return &activityRecorder; } 141}; 142 143} 144 145#endif /* __CPU_MINOR_PIPELINE_HH__ */ | 134 /** Functions below here are BaseCPU operations passed on to pipeline 135 * stages */ 136 137 /** Return the IcachePort belonging to Fetch1 for the CPU */ 138 MinorCPU::MinorCPUPort &getInstPort(); 139 /** Return the DcachePort belonging to Execute for the CPU */ 140 MinorCPU::MinorCPUPort &getDataPort(); 141 142 /** To give the activity recorder to the CPU */ 143 MinorActivityRecorder *getActivityRecorder() { return &activityRecorder; } 144}; 145 146} 147 148#endif /* __CPU_MINOR_PIPELINE_HH__ */ |