pipeline.hh (10259:ebb376f73dd2) pipeline.hh (10464:2a0fe8bca031)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 112 unchanged lines hidden (view full) ---

121
122 /** Test to see if the CPU is drained */
123 bool isDrained();
124
125 /** A custom evaluate allows report in the right place (between
126 * stages and pipeline advance) */
127 void evaluate();
128
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 112 unchanged lines hidden (view full) ---

121
122 /** Test to see if the CPU is drained */
123 bool isDrained();
124
125 /** A custom evaluate allows report in the right place (between
126 * stages and pipeline advance) */
127 void evaluate();
128
129 void countCycles(Cycles delta) M5_ATTR_OVERRIDE
130 {
131 cpu.ppCycles->notify(delta);
132 }
133
129 void minorTrace() const;
130
131 /** Functions below here are BaseCPU operations passed on to pipeline
132 * stages */
133
134 /** Return the IcachePort belonging to Fetch1 for the CPU */
135 MinorCPU::MinorCPUPort &getInstPort();
136 /** Return the DcachePort belonging to Execute for the CPU */
137 MinorCPU::MinorCPUPort &getDataPort();
138
139 /** To give the activity recorder to the CPU */
140 MinorActivityRecorder *getActivityRecorder() { return &activityRecorder; }
141};
142
143}
144
145#endif /* __CPU_MINOR_PIPELINE_HH__ */
134 void minorTrace() const;
135
136 /** Functions below here are BaseCPU operations passed on to pipeline
137 * stages */
138
139 /** Return the IcachePort belonging to Fetch1 for the CPU */
140 MinorCPU::MinorCPUPort &getInstPort();
141 /** Return the DcachePort belonging to Execute for the CPU */
142 MinorCPU::MinorCPUPort &getDataPort();
143
144 /** To give the activity recorder to the CPU */
145 MinorActivityRecorder *getActivityRecorder() { return &activityRecorder; }
146};
147
148}
149
150#endif /* __CPU_MINOR_PIPELINE_HH__ */