lsq.hh (13652:45d94ac03a27) lsq.hh (13954:2f400a5f2627)
1/*
1/*
2 * Copyright (c) 2013-2014 ARM Limited
2 * Copyright (c) 2013-2014, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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183 };
184
185 LSQRequestState state;
186
187 protected:
188 /** BaseTLB::Translation interface */
189 void markDelayed() { }
190
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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183 };
184
185 LSQRequestState state;
186
187 protected:
188 /** BaseTLB::Translation interface */
189 void markDelayed() { }
190
191 void disableMemAccess();
192
191 public:
192 LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
193 PacketDataPtr data_ = NULL, uint64_t *res_ = NULL);
194
195 virtual ~LSQRequest();
196
197 public:
198 /** Make a packet to use with the memory transaction */

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436
437 /** Step on numIssuedFragments */
438 void stepToNextPacket();
439
440 bool hasPacketsInMemSystem()
441 { return numIssuedFragments != numRetiredFragments; }
442
443 /** Have we stepped past the end of fragmentPackets? */
193 public:
194 LSQRequest(LSQ &port_, MinorDynInstPtr inst_, bool isLoad_,
195 PacketDataPtr data_ = NULL, uint64_t *res_ = NULL);
196
197 virtual ~LSQRequest();
198
199 public:
200 /** Make a packet to use with the memory transaction */

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438
439 /** Step on numIssuedFragments */
440 void stepToNextPacket();
441
442 bool hasPacketsInMemSystem()
443 { return numIssuedFragments != numRetiredFragments; }
444
445 /** Have we stepped past the end of fragmentPackets? */
444 bool sentAllPackets() { return numIssuedFragments == numFragments; }
446 bool sentAllPackets()
447 { return numIssuedFragments == numTranslatedFragments; }
445
446 /** For loads, paste the response data into the main
447 * response packet */
448 void retireResponse(PacketPtr packet_);
449
450 /** Part of the address translation loop, see startAddTranslation */
451 void sendNextFragmentToTranslation();
452 };

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695 * BarrierDataRequest and pushed it into the store buffer */
696 void completeMemBarrierInst(MinorDynInstPtr inst,
697 bool committed);
698
699 /** Single interface for readMem/writeMem/amoMem to issue requests into
700 * the LSQ */
701 void pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
702 unsigned int size, Addr addr, Request::Flags flags,
448
449 /** For loads, paste the response data into the main
450 * response packet */
451 void retireResponse(PacketPtr packet_);
452
453 /** Part of the address translation loop, see startAddTranslation */
454 void sendNextFragmentToTranslation();
455 };

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698 * BarrierDataRequest and pushed it into the store buffer */
699 void completeMemBarrierInst(MinorDynInstPtr inst,
700 bool committed);
701
702 /** Single interface for readMem/writeMem/amoMem to issue requests into
703 * the LSQ */
704 void pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
705 unsigned int size, Addr addr, Request::Flags flags,
703 uint64_t *res, AtomicOpFunctor *amo_op);
706 uint64_t *res, AtomicOpFunctor *amo_op,
707 const std::vector<bool>& byteEnable =
708 std::vector<bool>());
704
705 /** Push a predicate failed-representing request into the queues just
706 * to maintain commit order */
707 void pushFailedRequest(MinorDynInstPtr inst);
708
709 /** Memory interface */
710 bool recvTimingResp(PacketPtr pkt);
711 void recvReqRetry();

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710 /** Push a predicate failed-representing request into the queues just
711 * to maintain commit order */
712 void pushFailedRequest(MinorDynInstPtr inst);
713
714 /** Memory interface */
715 bool recvTimingResp(PacketPtr pkt);
716 void recvReqRetry();

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