lsq.hh (12748:ae5ce8e42de7) lsq.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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138
139 /* Requests carry packets on their way to the memory system.
140 * When a Packet returns from the memory system, its
141 * request needs to have its packet updated as this
142 * may have changed in flight */
143 PacketPtr packet;
144
145 /** The underlying request of this LSQRequest */
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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138
139 /* Requests carry packets on their way to the memory system.
140 * When a Packet returns from the memory system, its
141 * request needs to have its packet updated as this
142 * may have changed in flight */
143 PacketPtr packet;
144
145 /** The underlying request of this LSQRequest */
146 Request request;
146 RequestPtr request;
147
148 /** Fault generated performing this request */
149 Fault fault;
150
151 /** Res from pushRequest */
152 uint64_t *res;
153
154 /** Was skipped. Set to indicate any reason (faulted, bad

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267 LSQRequest::LSQRequestState state);
268
269 protected:
270 /** Special request types that don't actually issue memory requests */
271 class SpecialDataRequest : public LSQRequest
272 {
273 protected:
274 /** TLB interace */
147
148 /** Fault generated performing this request */
149 Fault fault;
150
151 /** Res from pushRequest */
152 uint64_t *res;
153
154 /** Was skipped. Set to indicate any reason (faulted, bad

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267 LSQRequest::LSQRequestState state);
268
269 protected:
270 /** Special request types that don't actually issue memory requests */
271 class SpecialDataRequest : public LSQRequest
272 {
273 protected:
274 /** TLB interace */
275 void finish(const Fault &fault_, RequestPtr request_,
275 void finish(const Fault &fault_, const RequestPtr &request_,
276 ThreadContext *tc, BaseTLB::Mode mode)
277 { }
278
279 public:
280 /** Send single translation request */
281 void startAddrTranslation() { }
282
283 /** Get the head packet as counted by numIssuedFragments */

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328 { state = Complete; }
329 };
330
331 /** SingleDataRequest is used for requests that don't fragment */
332 class SingleDataRequest : public LSQRequest
333 {
334 protected:
335 /** TLB interace */
276 ThreadContext *tc, BaseTLB::Mode mode)
277 { }
278
279 public:
280 /** Send single translation request */
281 void startAddrTranslation() { }
282
283 /** Get the head packet as counted by numIssuedFragments */

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328 { state = Complete; }
329 };
330
331 /** SingleDataRequest is used for requests that don't fragment */
332 class SingleDataRequest : public LSQRequest
333 {
334 protected:
335 /** TLB interace */
336 void finish(const Fault &fault_, RequestPtr request_,
336 void finish(const Fault &fault_, const RequestPtr &request_,
337 ThreadContext *tc, BaseTLB::Mode mode);
338
339 /** Has my only packet been sent to the memory system but has not
340 * yet been responded to */
341 bool packetInFlight;
342
343 /** Has the packet been at least sent to the memory system? */
344 bool packetSent;

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401 * each fragment */
402 std::vector<RequestPtr> fragmentRequests;
403
404 /** Packets matching fragmentRequests to issue fragments to memory */
405 std::vector<Packet *> fragmentPackets;
406
407 protected:
408 /** TLB response interface */
337 ThreadContext *tc, BaseTLB::Mode mode);
338
339 /** Has my only packet been sent to the memory system but has not
340 * yet been responded to */
341 bool packetInFlight;
342
343 /** Has the packet been at least sent to the memory system? */
344 bool packetSent;

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401 * each fragment */
402 std::vector<RequestPtr> fragmentRequests;
403
404 /** Packets matching fragmentRequests to issue fragments to memory */
405 std::vector<Packet *> fragmentPackets;
406
407 protected:
408 /** TLB response interface */
409 void finish(const Fault &fault_, RequestPtr request_,
409 void finish(const Fault &fault_, const RequestPtr &request_,
410 ThreadContext *tc, BaseTLB::Mode mode);
411
412 public:
413 SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
414 bool isLoad_, PacketDataPtr data_ = NULL,
415 uint64_t *res_ = NULL);
416
417 ~SplitDataRequest();

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715 MinorCPU::MinorCPUPort &getDcachePort() { return dcachePort; }
716
717 void minorTrace() const;
718};
719
720/** Make a suitable packet for the given request. If the request is a store,
721 * data will be the payload data. If sender_state is NULL, it won't be
722 * pushed into the packet as senderState */
410 ThreadContext *tc, BaseTLB::Mode mode);
411
412 public:
413 SplitDataRequest(LSQ &port_, MinorDynInstPtr inst_,
414 bool isLoad_, PacketDataPtr data_ = NULL,
415 uint64_t *res_ = NULL);
416
417 ~SplitDataRequest();

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715 MinorCPU::MinorCPUPort &getDcachePort() { return dcachePort; }
716
717 void minorTrace() const;
718};
719
720/** Make a suitable packet for the given request. If the request is a store,
721 * data will be the payload data. If sender_state is NULL, it won't be
722 * pushed into the packet as senderState */
723PacketPtr makePacketForRequest(Request &request, bool isLoad,
723PacketPtr makePacketForRequest(const RequestPtr &request, bool isLoad,
724 Packet::SenderState *sender_state = NULL, PacketDataPtr data = NULL);
725}
726
727#endif /* __CPU_MINOR_NEW_LSQ_HH__ */
724 Packet::SenderState *sender_state = NULL, PacketDataPtr data = NULL);
725}
726
727#endif /* __CPU_MINOR_NEW_LSQ_HH__ */