lsq.hh (11331:cd5c48db28e6) lsq.hh (11341:bda2c39fd9fd)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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93 LSQ &lsq;
94
95 public:
96 DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) :
97 MinorCPU::MinorCPUPort(name, cpu), lsq(lsq_)
98 { }
99
100 protected:
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 84 unchanged lines hidden (view full) ---

93 LSQ &lsq;
94
95 public:
96 DcachePort(std::string name, LSQ &lsq_, MinorCPU &cpu) :
97 MinorCPU::MinorCPUPort(name, cpu), lsq(lsq_)
98 { }
99
100 protected:
101 bool recvTimingResp(PacketPtr pkt)
101 bool recvTimingResp(PacketPtr pkt) override
102 { return lsq.recvTimingResp(pkt); }
103
102 { return lsq.recvTimingResp(pkt); }
103
104 void recvReqRetry() { lsq.recvReqRetry(); }
104 void recvReqRetry() override { lsq.recvReqRetry(); }
105
106 bool isSnooping() const override { return true; }
107
105
106 bool isSnooping() const override { return true; }
107
108 void recvTimingSnoopReq(PacketPtr pkt)
108 void recvTimingSnoopReq(PacketPtr pkt) override
109 { return lsq.recvTimingSnoopReq(pkt); }
110
109 { return lsq.recvTimingSnoopReq(pkt); }
110
111 void recvFunctionalSnoop(PacketPtr pkt) { }
111 void recvFunctionalSnoop(PacketPtr pkt) override { }
112 };
113
114 DcachePort dcachePort;
115
116 public:
117 /** Derived SenderState to carry data access info. through address
118 * translation, the queues in this port and back from the memory
119 * system. */

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113
114 DcachePort dcachePort;
115
116 public:
117 /** Derived SenderState to carry data access info. through address
118 * translation, the queues in this port and back from the memory
119 * system. */

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