lsq.cc (12748:ae5ce8e42de7) lsq.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2013-2014,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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78 data(data_),
79 packet(NULL),
80 request(),
81 fault(NoFault),
82 res(res_),
83 skipped(false),
84 issuedToMemory(false),
85 state(NotIssued)
1/*
2 * Copyright (c) 2013-2014,2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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78 data(data_),
79 packet(NULL),
80 request(),
81 fault(NoFault),
82 res(res_),
83 skipped(false),
84 issuedToMemory(false),
85 state(NotIssued)
86{ }
86{
87 request = std::make_shared<Request>();
88}
87
88LSQ::AddrRangeCoverage
89LSQ::LSQRequest::containsAddrRangeOf(
90 Addr req1_addr, unsigned int req1_size,
91 Addr req2_addr, unsigned int req2_size)
92{
93 /* 'end' here means the address of the byte just past the request
94 * blocks */

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105 ret = PartialAddrRangeCoverage;
106
107 return ret;
108}
109
110LSQ::AddrRangeCoverage
111LSQ::LSQRequest::containsAddrRangeOf(LSQRequestPtr other_request)
112{
89
90LSQ::AddrRangeCoverage
91LSQ::LSQRequest::containsAddrRangeOf(
92 Addr req1_addr, unsigned int req1_size,
93 Addr req2_addr, unsigned int req2_size)
94{
95 /* 'end' here means the address of the byte just past the request
96 * blocks */

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107 ret = PartialAddrRangeCoverage;
108
109 return ret;
110}
111
112LSQ::AddrRangeCoverage
113LSQ::LSQRequest::containsAddrRangeOf(LSQRequestPtr other_request)
114{
113 return containsAddrRangeOf(request.getPaddr(), request.getSize(),
114 other_request->request.getPaddr(), other_request->request.getSize());
115 return containsAddrRangeOf(request->getPaddr(), request->getSize(),
116 other_request->request->getPaddr(), other_request->request->getSize());
115}
116
117bool
118LSQ::LSQRequest::isBarrier()
119{
120 return inst->isInst() && inst->staticInst->isMemBarrier();
121}
122

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223 DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n",
224 (is_last_barrier ? "last" : "a"), *inst);
225
226 if (is_last_barrier)
227 lastMemBarrier[inst->id.threadId] = 0;
228}
229
230void
117}
118
119bool
120LSQ::LSQRequest::isBarrier()
121{
122 return inst->isInst() && inst->staticInst->isMemBarrier();
123}
124

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225 DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n",
226 (is_last_barrier ? "last" : "a"), *inst);
227
228 if (is_last_barrier)
229 lastMemBarrier[inst->id.threadId] = 0;
230}
231
232void
231LSQ::SingleDataRequest::finish(const Fault &fault_, RequestPtr request_,
233LSQ::SingleDataRequest::finish(const Fault &fault_, const RequestPtr &request_,
232 ThreadContext *tc, BaseTLB::Mode mode)
233{
234 fault = fault_;
235
236 port.numAccessesInDTLB--;
237
238 DPRINTFS(MinorMem, (&port), "Received translation response for"
239 " request: %s\n", *inst);

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257
258 setState(LSQ::LSQRequest::InTranslation);
259
260 DPRINTFS(MinorMem, (&port), "Submitting DTLB request\n");
261 /* Submit the translation request. The response will come through
262 * finish/markDelayed on the LSQRequest as it bears the Translation
263 * interface */
264 thread->getDTBPtr()->translateTiming(
234 ThreadContext *tc, BaseTLB::Mode mode)
235{
236 fault = fault_;
237
238 port.numAccessesInDTLB--;
239
240 DPRINTFS(MinorMem, (&port), "Received translation response for"
241 " request: %s\n", *inst);

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259
260 setState(LSQ::LSQRequest::InTranslation);
261
262 DPRINTFS(MinorMem, (&port), "Submitting DTLB request\n");
263 /* Submit the translation request. The response will come through
264 * finish/markDelayed on the LSQRequest as it bears the Translation
265 * interface */
266 thread->getDTBPtr()->translateTiming(
265 &request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write));
267 request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write));
266}
267
268void
269LSQ::SingleDataRequest::retireResponse(PacketPtr packet_)
270{
271 DPRINTFS(MinorMem, (&port), "Retiring packet\n");
272 packet = packet_;
273 packetInFlight = false;
274 setState(Complete);
275}
276
277void
268}
269
270void
271LSQ::SingleDataRequest::retireResponse(PacketPtr packet_)
272{
273 DPRINTFS(MinorMem, (&port), "Retiring packet\n");
274 packet = packet_;
275 packetInFlight = false;
276 setState(Complete);
277}
278
279void
278LSQ::SplitDataRequest::finish(const Fault &fault_, RequestPtr request_,
280LSQ::SplitDataRequest::finish(const Fault &fault_, const RequestPtr &request_,
279 ThreadContext *tc, BaseTLB::Mode mode)
280{
281 fault = fault_;
282
283 port.numAccessesInDTLB--;
284
285 unsigned int M5_VAR_USED expected_fragment_index =
286 numTranslatedFragments;

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332 fragmentPackets()
333{
334 /* Don't know how many elements are needed until the request is
335 * populated by the caller. */
336}
337
338LSQ::SplitDataRequest::~SplitDataRequest()
339{
281 ThreadContext *tc, BaseTLB::Mode mode)
282{
283 fault = fault_;
284
285 port.numAccessesInDTLB--;
286
287 unsigned int M5_VAR_USED expected_fragment_index =
288 numTranslatedFragments;

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334 fragmentPackets()
335{
336 /* Don't know how many elements are needed until the request is
337 * populated by the caller. */
338}
339
340LSQ::SplitDataRequest::~SplitDataRequest()
341{
340 for (auto i = fragmentRequests.begin();
341 i != fragmentRequests.end(); i++)
342 {
343 delete *i;
344 }
345
346 for (auto i = fragmentPackets.begin();
347 i != fragmentPackets.end(); i++)
348 {
349 delete *i;
350 }
351}
352
353void
354LSQ::SplitDataRequest::makeFragmentRequests()
355{
342 for (auto i = fragmentPackets.begin();
343 i != fragmentPackets.end(); i++)
344 {
345 delete *i;
346 }
347}
348
349void
350LSQ::SplitDataRequest::makeFragmentRequests()
351{
356 Addr base_addr = request.getVaddr();
357 unsigned int whole_size = request.getSize();
352 Addr base_addr = request->getVaddr();
353 unsigned int whole_size = request->getSize();
358 unsigned int line_width = port.lineWidth;
359
360 unsigned int fragment_size;
361 Addr fragment_addr;
362
363 /* Assume that this transfer is across potentially many block snap
364 * boundaries:
365 *

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418 fragment_size = end_addr - fragment_addr;
419 is_last_fragment = true;
420 } else {
421 /* Middle fragments */
422 fragment_size = line_width;
423 }
424 }
425
354 unsigned int line_width = port.lineWidth;
355
356 unsigned int fragment_size;
357 Addr fragment_addr;
358
359 /* Assume that this transfer is across potentially many block snap
360 * boundaries:
361 *

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414 fragment_size = end_addr - fragment_addr;
415 is_last_fragment = true;
416 } else {
417 /* Middle fragments */
418 fragment_size = line_width;
419 }
420 }
421
426 RequestPtr fragment = new Request();
422 RequestPtr fragment = std::make_shared<Request>();
427
423
428 fragment->setContext(request.contextId());
424 fragment->setContext(request->contextId());
429 fragment->setVirt(0 /* asid */,
425 fragment->setVirt(0 /* asid */,
430 fragment_addr, fragment_size, request.getFlags(),
431 request.masterId(),
432 request.getPC());
426 fragment_addr, fragment_size, request->getFlags(),
427 request->masterId(),
428 request->getPC());
433
434 DPRINTFS(MinorMem, (&port), "Generating fragment addr: 0x%x size: %d"
435 " (whole request addr: 0x%x size: %d) %s\n",
436 fragment_addr, fragment_size, base_addr, whole_size,
437 (is_last_fragment ? "last fragment" : ""));
438
439 fragment_addr += fragment_size;
440
441 fragmentRequests.push_back(fragment);
442 }
443}
444
445void
446LSQ::SplitDataRequest::makeFragmentPackets()
447{
429
430 DPRINTFS(MinorMem, (&port), "Generating fragment addr: 0x%x size: %d"
431 " (whole request addr: 0x%x size: %d) %s\n",
432 fragment_addr, fragment_size, base_addr, whole_size,
433 (is_last_fragment ? "last fragment" : ""));
434
435 fragment_addr += fragment_size;
436
437 fragmentRequests.push_back(fragment);
438 }
439}
440
441void
442LSQ::SplitDataRequest::makeFragmentPackets()
443{
448 Addr base_addr = request.getVaddr();
444 Addr base_addr = request->getVaddr();
449
450 DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst);
451
452 for (unsigned int fragment_index = 0; fragment_index < numFragments;
453 fragment_index++)
454 {
455 RequestPtr fragment = fragmentRequests[fragment_index];
456

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471 request_data = new uint8_t[fragment_size];
472 std::memcpy(request_data, data + (fragment_addr - base_addr),
473 fragment_size);
474 }
475
476 assert(fragment->hasPaddr());
477
478 PacketPtr fragment_packet =
445
446 DPRINTFS(MinorMem, (&port), "Making packets for request: %s\n", *inst);
447
448 for (unsigned int fragment_index = 0; fragment_index < numFragments;
449 fragment_index++)
450 {
451 RequestPtr fragment = fragmentRequests[fragment_index];
452

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467 request_data = new uint8_t[fragment_size];
468 std::memcpy(request_data, data + (fragment_addr - base_addr),
469 fragment_size);
470 }
471
472 assert(fragment->hasPaddr());
473
474 PacketPtr fragment_packet =
479 makePacketForRequest(*fragment, isLoad, this, request_data);
475 makePacketForRequest(fragment, isLoad, this, request_data);
480
481 fragmentPackets.push_back(fragment_packet);
482 /* Accumulate flags in parent request */
476
477 fragmentPackets.push_back(fragment_packet);
478 /* Accumulate flags in parent request */
483 request.setFlags(fragment->getFlags());
479 request->setFlags(fragment->getFlags());
484 }
485
486 /* Might as well make the overall/response packet here */
487 /* Get the physical address for the whole request/packet from the first
488 * fragment */
480 }
481
482 /* Might as well make the overall/response packet here */
483 /* Get the physical address for the whole request/packet from the first
484 * fragment */
489 request.setPaddr(fragmentRequests[0]->getPaddr());
485 request->setPaddr(fragmentRequests[0]->getPaddr());
490 makePacket();
491}
492
493void
494LSQ::SplitDataRequest::startAddrTranslation()
495{
496 setState(LSQ::LSQRequest::InTranslation);
497

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530void
531LSQ::SplitDataRequest::retireResponse(PacketPtr response)
532{
533 assert(numRetiredFragments < numFragments);
534
535 DPRINTFS(MinorMem, (&port), "Retiring fragment addr: 0x%x size: %d"
536 " offset: 0x%x (retired fragment num: %d) %s\n",
537 response->req->getVaddr(), response->req->getSize(),
486 makePacket();
487}
488
489void
490LSQ::SplitDataRequest::startAddrTranslation()
491{
492 setState(LSQ::LSQRequest::InTranslation);
493

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526void
527LSQ::SplitDataRequest::retireResponse(PacketPtr response)
528{
529 assert(numRetiredFragments < numFragments);
530
531 DPRINTFS(MinorMem, (&port), "Retiring fragment addr: 0x%x size: %d"
532 " offset: 0x%x (retired fragment num: %d) %s\n",
533 response->req->getVaddr(), response->req->getSize(),
538 request.getVaddr() - response->req->getVaddr(),
534 request->getVaddr() - response->req->getVaddr(),
539 numRetiredFragments,
540 (fault == NoFault ? "" : fault->name()));
541
542 numRetiredFragments++;
543
544 if (skipped) {
545 /* Skip because we already knew the request had faulted or been
546 * skipped */

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551 setSkipped();
552 packet->copyError(response);
553 } else {
554 if (isLoad) {
555 if (!data) {
556 /* For a split transfer, a Packet must be constructed
557 * to contain all returning data. This is that packet's
558 * data */
535 numRetiredFragments,
536 (fault == NoFault ? "" : fault->name()));
537
538 numRetiredFragments++;
539
540 if (skipped) {
541 /* Skip because we already knew the request had faulted or been
542 * skipped */

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547 setSkipped();
548 packet->copyError(response);
549 } else {
550 if (isLoad) {
551 if (!data) {
552 /* For a split transfer, a Packet must be constructed
553 * to contain all returning data. This is that packet's
554 * data */
559 data = new uint8_t[request.getSize()];
555 data = new uint8_t[request->getSize()];
560 }
561
562 /* Populate the portion of the overall response data represented
563 * by the response fragment */
564 std::memcpy(
556 }
557
558 /* Populate the portion of the overall response data represented
559 * by the response fragment */
560 std::memcpy(
565 data + (response->req->getVaddr() - request.getVaddr()),
561 data + (response->req->getVaddr() - request->getVaddr()),
566 response->getConstPtr<uint8_t>(),
567 response->req->getSize());
568 }
569 }
570
571 /* Complete early if we're skipping are no more in-flight accesses */
572 if (skipped && !hasPacketsInMemSystem()) {
573 DPRINTFS(MinorMem, (&port), "Completed skipped burst\n");

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580 setState(Complete);
581
582 if (!skipped && isComplete()) {
583 DPRINTFS(MinorMem, (&port), "Completed burst %d\n", packet != NULL);
584
585 DPRINTFS(MinorMem, (&port), "Retired packet isRead: %d isWrite: %d"
586 " needsResponse: %d packetSize: %s requestSize: %s responseSize:"
587 " %s\n", packet->isRead(), packet->isWrite(),
562 response->getConstPtr<uint8_t>(),
563 response->req->getSize());
564 }
565 }
566
567 /* Complete early if we're skipping are no more in-flight accesses */
568 if (skipped && !hasPacketsInMemSystem()) {
569 DPRINTFS(MinorMem, (&port), "Completed skipped burst\n");

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576 setState(Complete);
577
578 if (!skipped && isComplete()) {
579 DPRINTFS(MinorMem, (&port), "Completed burst %d\n", packet != NULL);
580
581 DPRINTFS(MinorMem, (&port), "Retired packet isRead: %d isWrite: %d"
582 " needsResponse: %d packetSize: %s requestSize: %s responseSize:"
583 " %s\n", packet->isRead(), packet->isWrite(),
588 packet->needsResponse(), packet->getSize(), request.getSize(),
584 packet->needsResponse(), packet->getSize(), request->getSize(),
589 response->getSize());
590
591 /* A request can become complete by several paths, this is a sanity
592 * check to make sure the packet's data is created */
593 if (!data) {
585 response->getSize());
586
587 /* A request can become complete by several paths, this is a sanity
588 * check to make sure the packet's data is created */
589 if (!data) {
594 data = new uint8_t[request.getSize()];
590 data = new uint8_t[request->getSize()];
595 }
596
597 if (isLoad) {
598 DPRINTFS(MinorMem, (&port), "Copying read data\n");
591 }
592
593 if (isLoad) {
594 DPRINTFS(MinorMem, (&port), "Copying read data\n");
599 std::memcpy(packet->getPtr<uint8_t>(), data, request.getSize());
595 std::memcpy(packet->getPtr<uint8_t>(), data, request->getSize());
600 }
601 packet->makeResponse();
602 }
603
604 /* Packets are all deallocated together in ~SplitLSQRequest */
605}
606
607void

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686 slot->inst->id.threadId == request->inst->id.threadId &&
687 !slot->packet->req->isCacheMaintenance()) {
688 AddrRangeCoverage coverage = slot->containsAddrRangeOf(request);
689
690 if (coverage != NoAddrRangeCoverage) {
691 DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:"
692 " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n",
693 slot_index, coverage,
596 }
597 packet->makeResponse();
598 }
599
600 /* Packets are all deallocated together in ~SplitLSQRequest */
601}
602
603void

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682 slot->inst->id.threadId == request->inst->id.threadId &&
683 !slot->packet->req->isCacheMaintenance()) {
684 AddrRangeCoverage coverage = slot->containsAddrRangeOf(request);
685
686 if (coverage != NoAddrRangeCoverage) {
687 DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:"
688 " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n",
689 slot_index, coverage,
694 request->request.getPaddr(), request->request.getSize(),
695 slot->request.getPaddr(), slot->request.getSize());
690 request->request->getPaddr(), request->request->getSize(),
691 slot->request->getPaddr(), slot->request->getSize());
696
697 found_slot = slot_index;
698 ret = coverage;
699 }
700 }
701
702 i++;
703 slot_index--;

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715 assert(load->packet);
716 assert(load->isLoad);
717
718 LSQRequestPtr store = slots[slot_number];
719
720 assert(store->packet);
721 assert(store->containsAddrRangeOf(load) == FullAddrRangeCoverage);
722
692
693 found_slot = slot_index;
694 ret = coverage;
695 }
696 }
697
698 i++;
699 slot_index--;

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711 assert(load->packet);
712 assert(load->isLoad);
713
714 LSQRequestPtr store = slots[slot_number];
715
716 assert(store->packet);
717 assert(store->containsAddrRangeOf(load) == FullAddrRangeCoverage);
718
723 Addr load_addr = load->request.getPaddr();
724 Addr store_addr = store->request.getPaddr();
719 Addr load_addr = load->request->getPaddr();
720 Addr store_addr = store->request->getPaddr();
725 Addr addr_offset = load_addr - store_addr;
726
721 Addr addr_offset = load_addr - store_addr;
722
727 unsigned int load_size = load->request.getSize();
723 unsigned int load_size = load->request->getSize();
728
729 DPRINTF(MinorMem, "Forwarding %d bytes for addr: 0x%x from store buffer"
730 " slot: %d addr: 0x%x addressOffset: 0x%x\n",
731 load_size, load_addr, slot_number,
732 store_addr, addr_offset);
733
734 void *load_packet_data = load->packet->getPtr<void>();
735 void *store_packet_data = store->packet->getPtr<uint8_t>() + addr_offset;

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927 " queue\n");
928 request->setState(LSQRequest::Complete);
929 request->setSkipped();
930 moveFromRequestsToTransfers(request);
931 return;
932 }
933
934 bool is_load = request->isLoad;
724
725 DPRINTF(MinorMem, "Forwarding %d bytes for addr: 0x%x from store buffer"
726 " slot: %d addr: 0x%x addressOffset: 0x%x\n",
727 load_size, load_addr, slot_number,
728 store_addr, addr_offset);
729
730 void *load_packet_data = load->packet->getPtr<void>();
731 void *store_packet_data = store->packet->getPtr<uint8_t>() + addr_offset;

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923 " queue\n");
924 request->setState(LSQRequest::Complete);
925 request->setSkipped();
926 moveFromRequestsToTransfers(request);
927 return;
928 }
929
930 bool is_load = request->isLoad;
935 bool is_llsc = request->request.isLLSC();
936 bool is_swap = request->request.isSwap();
937 bool bufferable = !(request->request.isStrictlyOrdered() ||
931 bool is_llsc = request->request->isLLSC();
932 bool is_swap = request->request->isSwap();
933 bool bufferable = !(request->request->isStrictlyOrdered() ||
938 is_llsc || is_swap);
939
940 if (is_load) {
941 if (numStoresInTransfers != 0) {
942 DPRINTF(MinorMem, "Load request with stores still in transfers"
943 " queue, stalling\n");
944 return;
945 }
946 } else {
947 /* Store. Can it be sent to the store buffer? */
934 is_llsc || is_swap);
935
936 if (is_load) {
937 if (numStoresInTransfers != 0) {
938 DPRINTF(MinorMem, "Load request with stores still in transfers"
939 " queue, stalling\n");
940 return;
941 }
942 } else {
943 /* Store. Can it be sent to the store buffer? */
948 if (bufferable && !request->request.isMmappedIpr()) {
944 if (bufferable && !request->request->isMmappedIpr()) {
949 request->setState(LSQRequest::StoreToStoreBuffer);
950 moveFromRequestsToTransfers(request);
951 DPRINTF(MinorMem, "Moving store into transfers queue\n");
952 return;
953 }
954 }
955
956 /* Check if this is the head instruction (and so must be executable as

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1018
1019 SimpleThread &thread = *cpu.threads[request->inst->id.threadId];
1020
1021 TheISA::PCState old_pc = thread.pcState();
1022 ExecContext context(cpu, thread, execute, request->inst);
1023
1024 /* Handle LLSC requests and tests */
1025 if (is_load) {
945 request->setState(LSQRequest::StoreToStoreBuffer);
946 moveFromRequestsToTransfers(request);
947 DPRINTF(MinorMem, "Moving store into transfers queue\n");
948 return;
949 }
950 }
951
952 /* Check if this is the head instruction (and so must be executable as

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1014
1015 SimpleThread &thread = *cpu.threads[request->inst->id.threadId];
1016
1017 TheISA::PCState old_pc = thread.pcState();
1018 ExecContext context(cpu, thread, execute, request->inst);
1019
1020 /* Handle LLSC requests and tests */
1021 if (is_load) {
1026 TheISA::handleLockedRead(&context, &request->request);
1022 TheISA::handleLockedRead(&context, request->request);
1027 } else {
1028 do_access = TheISA::handleLockedWrite(&context,
1023 } else {
1024 do_access = TheISA::handleLockedWrite(&context,
1029 &request->request, cacheBlockMask);
1025 request->request, cacheBlockMask);
1030
1031 if (!do_access) {
1032 DPRINTF(MinorMem, "Not perfoming a memory "
1033 "access for store conditional\n");
1034 }
1035 }
1036 thread.pcState(old_pc);
1037 }

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1072
1073 DPRINTF(MinorMem, "Trying to send request: %s addr: 0x%x\n",
1074 *(request->inst), packet->req->getVaddr());
1075
1076 /* The sender state of the packet *must* be an LSQRequest
1077 * so the response can be correctly handled */
1078 assert(packet->findNextSenderState<LSQRequest>());
1079
1026
1027 if (!do_access) {
1028 DPRINTF(MinorMem, "Not perfoming a memory "
1029 "access for store conditional\n");
1030 }
1031 }
1032 thread.pcState(old_pc);
1033 }

--- 34 unchanged lines hidden (view full) ---

1068
1069 DPRINTF(MinorMem, "Trying to send request: %s addr: 0x%x\n",
1070 *(request->inst), packet->req->getVaddr());
1071
1072 /* The sender state of the packet *must* be an LSQRequest
1073 * so the response can be correctly handled */
1074 assert(packet->findNextSenderState<LSQRequest>());
1075
1080 if (request->request.isMmappedIpr()) {
1076 if (request->request->isMmappedIpr()) {
1081 ThreadContext *thread =
1082 cpu.getContext(cpu.contextToThread(
1077 ThreadContext *thread =
1078 cpu.getContext(cpu.contextToThread(
1083 request->request.contextId()));
1079 request->request->contextId()));
1084
1085 if (request->isLoad) {
1086 DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
1087 TheISA::handleIprRead(thread, packet);
1088 } else {
1089 DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst));
1090 TheISA::handleIprWrite(thread, packet);
1091 }

--- 419 unchanged lines hidden (view full) ---

1511 request = new SingleDataRequest(
1512 *this, inst, isLoad, request_data, res);
1513 }
1514
1515 if (inst->traceData)
1516 inst->traceData->setMem(addr, size, flags);
1517
1518 int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
1080
1081 if (request->isLoad) {
1082 DPRINTF(MinorMem, "IPR read inst: %s\n", *(request->inst));
1083 TheISA::handleIprRead(thread, packet);
1084 } else {
1085 DPRINTF(MinorMem, "IPR write inst: %s\n", *(request->inst));
1086 TheISA::handleIprWrite(thread, packet);
1087 }

--- 419 unchanged lines hidden (view full) ---

1507 request = new SingleDataRequest(
1508 *this, inst, isLoad, request_data, res);
1509 }
1510
1511 if (inst->traceData)
1512 inst->traceData->setMem(addr, size, flags);
1513
1514 int cid = cpu.threads[inst->id.threadId]->getTC()->contextId();
1519 request->request.setContext(cid);
1520 request->request.setVirt(0 /* asid */,
1515 request->request->setContext(cid);
1516 request->request->setVirt(0 /* asid */,
1521 addr, size, flags, cpu.dataMasterId(),
1522 /* I've no idea why we need the PC, but give it */
1523 inst->pc.instAddr());
1524
1525 requests.push(request);
1526 request->startAddrTranslation();
1527}
1528

--- 23 unchanged lines hidden (view full) ---

1552 numSlots(store_buffer_size),
1553 storeLimitPerCycle(store_limit_per_cycle),
1554 slots(),
1555 numUnissuedAccesses(0)
1556{
1557}
1558
1559PacketPtr
1517 addr, size, flags, cpu.dataMasterId(),
1518 /* I've no idea why we need the PC, but give it */
1519 inst->pc.instAddr());
1520
1521 requests.push(request);
1522 request->startAddrTranslation();
1523}
1524

--- 23 unchanged lines hidden (view full) ---

1548 numSlots(store_buffer_size),
1549 storeLimitPerCycle(store_limit_per_cycle),
1550 slots(),
1551 numUnissuedAccesses(0)
1552{
1553}
1554
1555PacketPtr
1560makePacketForRequest(Request &request, bool isLoad,
1556makePacketForRequest(const RequestPtr &request, bool isLoad,
1561 Packet::SenderState *sender_state, PacketDataPtr data)
1562{
1557 Packet::SenderState *sender_state, PacketDataPtr data)
1558{
1563 PacketPtr ret = isLoad ? Packet::createRead(&request)
1564 : Packet::createWrite(&request);
1559 PacketPtr ret = isLoad ? Packet::createRead(request)
1560 : Packet::createWrite(request);
1565
1566 if (sender_state)
1567 ret->pushSenderState(sender_state);
1568
1569 if (isLoad) {
1570 ret->allocate();
1561
1562 if (sender_state)
1563 ret->pushSenderState(sender_state);
1564
1565 if (isLoad) {
1566 ret->allocate();
1571 } else if (!request.isCacheMaintenance()) {
1567 } else if (!request->isCacheMaintenance()) {
1572 // CMOs are treated as stores but they don't have data. All
1573 // stores otherwise need to allocate for data.
1574 ret->dataDynamic(data);
1575 }
1576
1577 return ret;
1578}
1579

--- 93 unchanged lines hidden --- 		1568 // CMOs are treated as stores but they don't have data. All
1569 // stores otherwise need to allocate for data.
1570 ret->dataDynamic(data);
1571 }
1572
1573 return ret;
1574}
1575

--- 93 unchanged lines hidden ---