1/* 2 * Copyright (c) 2013-2014,2017 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 30 unchanged lines hidden (view full) --- 39 40#include "cpu/minor/lsq.hh" 41 42#include <iomanip> 43#include <sstream> 44 45#include "arch/locked_mem.hh" 46#include "arch/mmapped_ipr.hh" |
47#include "base/logging.hh" |
48#include "cpu/minor/cpu.hh" 49#include "cpu/minor/exec_context.hh" 50#include "cpu/minor/execute.hh" 51#include "cpu/minor/pipeline.hh" 52#include "debug/Activity.hh" 53#include "debug/MinorMem.hh" 54 55namespace Minor --- 1061 unchanged lines hidden (view full) --- 1117 break; 1118 case LSQRequest::StoreInStoreBuffer: 1119 case LSQRequest::StoreBufferIssuing: 1120 /* Fully or partially issued a request in the store 1121 * buffer */ 1122 request->setState(LSQRequest::StoreBufferIssuing); 1123 break; 1124 default: |
1125 panic("Unrecognized LSQ request state %d.", request->state); |
1126 } 1127 1128 state = MemoryRunning; 1129 } else { 1130 DPRINTF(MinorMem, 1131 "Sending data memory request - needs retry\n"); 1132 1133 /* Needs to be resent, wait for that */ --- 5 unchanged lines hidden (view full) --- 1139 case LSQRequest::RequestIssuing: 1140 request->setState(LSQRequest::RequestNeedsRetry); 1141 break; 1142 case LSQRequest::StoreInStoreBuffer: 1143 case LSQRequest::StoreBufferIssuing: 1144 request->setState(LSQRequest::StoreBufferNeedsRetry); 1145 break; 1146 default: |
1147 panic("Unrecognized LSQ request state %d.", request->state); |
1148 } 1149 } 1150 } 1151 1152 if (ret) 1153 threadSnoop(request); 1154 1155 return ret; --- 64 unchanged lines hidden (view full) --- 1220 } else { 1221 DPRINTF(MinorMem, "Completed transfer for barrier: %s" 1222 " leaving the request as it is also a barrier\n", 1223 *(request->inst)); 1224 } 1225 } 1226 break; 1227 default: |
1228 panic("Shouldn't be allowed to receive a response from another state"); |
1229 } 1230 1231 /* We go to idle even if there are more things in the requests queue 1232 * as it's the job of step to actually step us on to the next 1233 * transaction */ 1234 1235 /* Let's try and wake up the processor for the next cycle */ 1236 cpu.wakeupOnEvent(Pipeline::ExecuteStageId); --- 14 unchanged lines hidden (view full) --- 1251 /* Retry in the requests queue */ 1252 retryRequest->setState(LSQRequest::Translated); 1253 break; 1254 case LSQRequest::StoreBufferNeedsRetry: 1255 /* Retry in the store buffer */ 1256 retryRequest->setState(LSQRequest::StoreInStoreBuffer); 1257 break; 1258 default: |
1259 panic("Unrecognized retry request state %d.", retryRequest->state); |
1260 } 1261 1262 /* Set state back to MemoryRunning so that the following 1263 * tryToSend can actually send. Note that this won't 1264 * allow another transfer in as tryToSend should 1265 * issue a memory request and either succeed for this 1266 * request or return the LSQ back to MemoryNeedsRetry */ 1267 state = MemoryRunning; --- 6 unchanged lines hidden (view full) --- 1274 /* In the requests queue */ 1275 moveFromRequestsToTransfers(retryRequest); 1276 break; 1277 case LSQRequest::StoreBufferIssuing: 1278 /* In the store buffer */ 1279 storeBuffer.countIssuedStore(retryRequest); 1280 break; 1281 default: |
1282 panic("Unrecognized retry request state %d.", retryRequest->state); |
1283 } 1284 1285 retryRequest = NULL; 1286 } 1287} 1288 1289LSQ::LSQ(std::string name_, std::string dcache_port_name_, 1290 MinorCPU &cpu_, Execute &execute_, --- 373 unchanged lines hidden --- |