1/* |
2 * Copyright (c) 2013-2014,2017 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 663 unchanged lines hidden (view full) --- 674 auto i = slots.rbegin(); 675 AddrRangeCoverage ret = NoAddrRangeCoverage; 676 677 /* Traverse the store buffer in reverse order (most to least recent) 678 * and try to find a slot whose address range overlaps this request */ 679 while (ret == NoAddrRangeCoverage && i != slots.rend()) { 680 LSQRequestPtr slot = *i; 681 |
682 /* Cache maintenance instructions go down via the store path * 683 * but they carry no data and they shouldn't be considered for 684 * forwarding */ |
685 if (slot->packet && |
686 slot->inst->id.threadId == request->inst->id.threadId && 687 !slot->packet->req->isCacheMaintenance()) { |
688 AddrRangeCoverage coverage = slot->containsAddrRangeOf(request); 689 690 if (coverage != NoAddrRangeCoverage) { 691 DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:" 692 " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n", 693 slot_index, coverage, 694 request->request.getPaddr(), request->request.getSize(), 695 slot->request.getPaddr(), slot->request.getSize()); --- 795 unchanged lines hidden (view full) --- 1491 " 0x%x%s lineWidth : 0x%x\n", 1492 (isLoad ? "load" : "store"), addr, size, flags, 1493 (needs_burst ? " (needs burst)" : ""), lineWidth); 1494 1495 if (!isLoad) { 1496 /* request_data becomes the property of a ...DataRequest (see below) 1497 * and destroyed by its destructor */ 1498 request_data = new uint8_t[size]; |
1499 if (flags & Request::STORE_NO_DATA) { |
1500 /* For cache zeroing, just use zeroed data */ 1501 std::memset(request_data, 0, size); 1502 } else { 1503 std::memcpy(request_data, data, size); 1504 } 1505 } 1506 1507 if (needs_burst) { --- 53 unchanged lines hidden (view full) --- 1561 Packet::SenderState *sender_state, PacketDataPtr data) 1562{ 1563 PacketPtr ret = isLoad ? Packet::createRead(&request) 1564 : Packet::createWrite(&request); 1565 1566 if (sender_state) 1567 ret->pushSenderState(sender_state); 1568 |
1569 if (isLoad) { |
1570 ret->allocate(); |
1571 } else if (!request.isCacheMaintenance()) { 1572 // CMOs are treated as stores but they don't have data. All 1573 // stores otherwise need to allocate for data. |
1574 ret->dataDynamic(data); |
1575 } |
1576 1577 return ret; 1578} 1579 1580void 1581LSQ::issuedMemBarrierInst(MinorDynInstPtr inst) 1582{ 1583 assert(inst->isInst() && inst->staticInst->isMemBarrier()); --- 89 unchanged lines hidden --- |