1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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674 auto i = slots.rbegin();
675 AddrRangeCoverage ret = NoAddrRangeCoverage;
676
677 /* Traverse the store buffer in reverse order (most to least recent)
678 * and try to find a slot whose address range overlaps this request */
679 while (ret == NoAddrRangeCoverage && i != slots.rend()) {
680 LSQRequestPtr slot = *i;
681
682 if (slot->packet &&
683 slot->inst->id.threadId == request->inst->id.threadId) {
684 AddrRangeCoverage coverage = slot->containsAddrRangeOf(request);
685
686 if (coverage != NoAddrRangeCoverage) {
687 DPRINTF(MinorMem, "Forwarding: slot: %d result: %s thisAddr:"
688 " 0x%x thisSize: %d slotAddr: 0x%x slotSize: %d\n",
689 slot_index, coverage,
690 request->request.getPaddr(), request->request.getSize(),
691 slot->request.getPaddr(), slot->request.getSize());

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1487 " 0x%x%s lineWidth : 0x%x\n",
1488 (isLoad ? "load" : "store"), addr, size, flags,
1489 (needs_burst ? " (needs burst)" : ""), lineWidth);
1490
1491 if (!isLoad) {
1492 /* request_data becomes the property of a ...DataRequest (see below)
1493 * and destroyed by its destructor */
1494 request_data = new uint8_t[size];
1495 if (flags & Request::CACHE_BLOCK_ZERO) {
1496 /* For cache zeroing, just use zeroed data */
1497 std::memset(request_data, 0, size);
1498 } else {
1499 std::memcpy(request_data, data, size);
1500 }
1501 }
1502
1503 if (needs_burst) {

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1557 Packet::SenderState *sender_state, PacketDataPtr data)
1558{
1559 PacketPtr ret = isLoad ? Packet::createRead(&request)
1560 : Packet::createWrite(&request);
1561
1562 if (sender_state)
1563 ret->pushSenderState(sender_state);
1564
1565 if (isLoad)
1566 ret->allocate();
1567 else
1568 ret->dataDynamic(data);
1569
1570 return ret;
1571}
1572
1573void
1574LSQ::issuedMemBarrierInst(MinorDynInstPtr inst)
1575{
1576 assert(inst->isInst() && inst->staticInst->isMemBarrier());

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