fetch2.cc (12324:6142a2fec8d9) | fetch2.cc (13632:483aaa00c69c) |
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1/* 2 * Copyright (c) 2013-2014,2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 106 unchanged lines hidden (view full) --- 115void 116Fetch2::dumpAllInput(ThreadID tid) 117{ 118 DPRINTF(Fetch, "Dumping whole input buffer\n"); 119 while (!inputBuffer[tid].empty()) 120 popInput(tid); 121 122 fetchInfo[tid].inputIndex = 0; | 1/* 2 * Copyright (c) 2013-2014,2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 106 unchanged lines hidden (view full) --- 115void 116Fetch2::dumpAllInput(ThreadID tid) 117{ 118 DPRINTF(Fetch, "Dumping whole input buffer\n"); 119 while (!inputBuffer[tid].empty()) 120 popInput(tid); 121 122 fetchInfo[tid].inputIndex = 0; |
123 fetchInfo[tid].havePC = false; |
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123} 124 125void 126Fetch2::updateBranchPrediction(const BranchData &branch) 127{ 128 MinorDynInstPtr inst = branch.inst; 129 130 /* Don't even consider instructions we didn't try to predict or faults */ --- 523 unchanged lines hidden --- | 124} 125 126void 127Fetch2::updateBranchPrediction(const BranchData &branch) 128{ 129 MinorDynInstPtr inst = branch.inst; 130 131 /* Don't even consider instructions we didn't try to predict or faults */ --- 523 unchanged lines hidden --- |