fetch2.cc (10537:47fe87b0cf97) fetch2.cc (11567:560d7fbbddd1)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53
54Fetch2::Fetch2(const std::string &name,
55 MinorCPU &cpu_,
56 MinorCPUParams &params,
57 Latch<ForwardLineData>::Output inp_,
58 Latch<BranchData>::Output branchInp_,
59 Latch<BranchData>::Input predictionOut_,
60 Latch<ForwardInstData>::Input out_,
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 44 unchanged lines hidden (view full) ---

53
54Fetch2::Fetch2(const std::string &name,
55 MinorCPU &cpu_,
56 MinorCPUParams &params,
57 Latch<ForwardLineData>::Output inp_,
58 Latch<BranchData>::Output branchInp_,
59 Latch<BranchData>::Input predictionOut_,
60 Latch<ForwardInstData>::Input out_,
61 Reservable &next_stage_input_buffer) :
61 std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer) :
62 Named(name),
63 cpu(cpu_),
64 inp(inp_),
65 branchInp(branchInp_),
66 predictionOut(predictionOut_),
67 out(out_),
68 nextStageReserve(next_stage_input_buffer),
69 outputWidth(params.decodeInputWidth),
70 processMoreThanOneInput(params.fetch2CycleInput),
71 branchPredictor(*params.branchPred),
62 Named(name),
63 cpu(cpu_),
64 inp(inp_),
65 branchInp(branchInp_),
66 predictionOut(predictionOut_),
67 out(out_),
68 nextStageReserve(next_stage_input_buffer),
69 outputWidth(params.decodeInputWidth),
70 processMoreThanOneInput(params.fetch2CycleInput),
71 branchPredictor(*params.branchPred),
72 inputBuffer(name + ".inputBuffer", "lines", params.fetch2InputBufferSize),
73 inputIndex(0),
74 pc(TheISA::PCState(0)),
75 havePC(false),
76 lastStreamSeqNum(InstId::firstStreamSeqNum),
77 fetchSeqNum(InstId::firstFetchSeqNum),
78 expectedStreamSeqNum(InstId::firstStreamSeqNum),
79 predictionSeqNum(InstId::firstPredictionSeqNum),
80 blocked(false)
72 fetchInfo(params.numThreads),
73 threadPriority(0)
81{
82 if (outputWidth < 1)
83 fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name, outputWidth);
84
85 if (params.fetch2InputBufferSize < 1) {
86 fatal("%s: fetch2InputBufferSize must be >= 1 (%d)\n", name,
87 params.fetch2InputBufferSize);
88 }
74{
75 if (outputWidth < 1)
76 fatal("%s: decodeInputWidth must be >= 1 (%d)\n", name, outputWidth);
77
78 if (params.fetch2InputBufferSize < 1) {
79 fatal("%s: fetch2InputBufferSize must be >= 1 (%d)\n", name,
80 params.fetch2InputBufferSize);
81 }
82
83 /* Per-thread input buffers */
84 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
85 inputBuffer.push_back(
86 InputBuffer<ForwardLineData>(
87 name + ".inputBuffer" + std::to_string(tid), "lines",
88 params.fetch2InputBufferSize));
89 }
89}
90
91const ForwardLineData *
90}
91
92const ForwardLineData *
92Fetch2::getInput()
93Fetch2::getInput(ThreadID tid)
93{
94 /* Get a line from the inputBuffer to work with */
94{
95 /* Get a line from the inputBuffer to work with */
95 if (!inputBuffer.empty()) {
96 return &(inputBuffer.front());
96 if (!inputBuffer[tid].empty()) {
97 return &(inputBuffer[tid].front());
97 } else {
98 return NULL;
99 }
100}
101
102void
98 } else {
99 return NULL;
100 }
101}
102
103void
103Fetch2::popInput()
104Fetch2::popInput(ThreadID tid)
104{
105{
105 if (!inputBuffer.empty()) {
106 inputBuffer.front().freeLine();
107 inputBuffer.pop();
106 if (!inputBuffer[tid].empty()) {
107 inputBuffer[tid].front().freeLine();
108 inputBuffer[tid].pop();
108 }
109
109 }
110
110 inputIndex = 0;
111 fetchInfo[tid].inputIndex = 0;
111}
112
113void
112}
113
114void
114Fetch2::dumpAllInput()
115Fetch2::dumpAllInput(ThreadID tid)
115{
116 DPRINTF(Fetch, "Dumping whole input buffer\n");
116{
117 DPRINTF(Fetch, "Dumping whole input buffer\n");
117 while (!inputBuffer.empty())
118 popInput();
118 while (!inputBuffer[tid].empty())
119 popInput(tid);
119
120
120 inputIndex = 0;
121 fetchInfo[tid].inputIndex = 0;
121}
122
123void
124Fetch2::updateBranchPrediction(const BranchData &branch)
125{
126 MinorDynInstPtr inst = branch.inst;
127
128 /* Don't even consider instructions we didn't try to predict or faults */

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134 /* No data to update */
135 break;
136 case BranchData::Interrupt:
137 /* Never try to predict interrupts */
138 break;
139 case BranchData::SuspendThread:
140 /* Don't need to act on suspends */
141 break;
122}
123
124void
125Fetch2::updateBranchPrediction(const BranchData &branch)
126{
127 MinorDynInstPtr inst = branch.inst;
128
129 /* Don't even consider instructions we didn't try to predict or faults */

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135 /* No data to update */
136 break;
137 case BranchData::Interrupt:
138 /* Never try to predict interrupts */
139 break;
140 case BranchData::SuspendThread:
141 /* Don't need to act on suspends */
142 break;
142 case BranchData::WakeupFetch:
143 /* Don't need to act on wakeups, no instruction tied to action. */
144 break;
145 case BranchData::HaltFetch:
146 /* Don't need to act on fetch wakeup */
147 break;
148 case BranchData::BranchPrediction:
149 /* Shouldn't happen. Fetch2 is the only source of
150 * BranchPredictions */
151 break;
152 case BranchData::UnpredictedBranch:

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175 branch.target, true, inst->id.threadId);
176 break;
177 }
178}
179
180void
181Fetch2::predictBranch(MinorDynInstPtr inst, BranchData &branch)
182{
143 case BranchData::HaltFetch:
144 /* Don't need to act on fetch wakeup */
145 break;
146 case BranchData::BranchPrediction:
147 /* Shouldn't happen. Fetch2 is the only source of
148 * BranchPredictions */
149 break;
150 case BranchData::UnpredictedBranch:

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173 branch.target, true, inst->id.threadId);
174 break;
175 }
176}
177
178void
179Fetch2::predictBranch(MinorDynInstPtr inst, BranchData &branch)
180{
181 Fetch2ThreadInfo &thread = fetchInfo[inst->id.threadId];
183 TheISA::PCState inst_pc = inst->pc;
184
185 assert(!inst->predictedTaken);
186
187 /* Skip non-control/sys call instructions */
188 if (inst->staticInst->isControl() ||
189 inst->staticInst->isSyscall())
190 {

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204 } else {
205 DPRINTF(Branch, "Not attempting prediction for inst: %s\n", *inst);
206 }
207
208 /* If we predict taken, set branch and update sequence numbers */
209 if (inst->predictedTaken) {
210 /* Update the predictionSeqNum and remember the streamSeqNum that it
211 * was associated with */
182 TheISA::PCState inst_pc = inst->pc;
183
184 assert(!inst->predictedTaken);
185
186 /* Skip non-control/sys call instructions */
187 if (inst->staticInst->isControl() ||
188 inst->staticInst->isSyscall())
189 {

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203 } else {
204 DPRINTF(Branch, "Not attempting prediction for inst: %s\n", *inst);
205 }
206
207 /* If we predict taken, set branch and update sequence numbers */
208 if (inst->predictedTaken) {
209 /* Update the predictionSeqNum and remember the streamSeqNum that it
210 * was associated with */
212 expectedStreamSeqNum = inst->id.streamSeqNum;
211 thread.expectedStreamSeqNum = inst->id.streamSeqNum;
213
214 BranchData new_branch = BranchData(BranchData::BranchPrediction,
212
213 BranchData new_branch = BranchData(BranchData::BranchPrediction,
215 inst->id.streamSeqNum, predictionSeqNum + 1,
214 inst->id.threadId,
215 inst->id.streamSeqNum, thread.predictionSeqNum + 1,
216 inst->predictedTarget, inst);
217
218 /* Mark with a new prediction number by the stream number of the
219 * instruction causing the prediction */
216 inst->predictedTarget, inst);
217
218 /* Mark with a new prediction number by the stream number of the
219 * instruction causing the prediction */
220 predictionSeqNum++;
220 thread.predictionSeqNum++;
221 branch = new_branch;
222
223 DPRINTF(Branch, "Branch predicted taken inst: %s target: %s"
224 " new predictionSeqNum: %d\n",
221 branch = new_branch;
222
223 DPRINTF(Branch, "Branch predicted taken inst: %s target: %s"
224 " new predictionSeqNum: %d\n",
225 *inst, inst->predictedTarget, predictionSeqNum);
225 *inst, inst->predictedTarget, thread.predictionSeqNum);
226 }
227}
228
229void
230Fetch2::evaluate()
231{
226 }
227}
228
229void
230Fetch2::evaluate()
231{
232 inputBuffer.setTail(*inp.outputWire);
232 /* Push input onto appropriate input buffer */
233 if (!inp.outputWire->isBubble())
234 inputBuffer[inp.outputWire->id.threadId].setTail(*inp.outputWire);
235
233 ForwardInstData &insts_out = *out.inputWire;
234 BranchData prediction;
235 BranchData &branch_inp = *branchInp.outputWire;
236
237 assert(insts_out.isBubble());
238
236 ForwardInstData &insts_out = *out.inputWire;
237 BranchData prediction;
238 BranchData &branch_inp = *branchInp.outputWire;
239
240 assert(insts_out.isBubble());
241
239 blocked = false;
240
241 /* React to branches from Execute to update local branch prediction
242 * structures */
243 updateBranchPrediction(branch_inp);
244
245 /* If a branch arrives, don't try and do anything about it. Only
246 * react to your own predictions */
247 if (branch_inp.isStreamChange()) {
248 DPRINTF(Fetch, "Dumping all input as a stream changing branch"
249 " has arrived\n");
242 /* React to branches from Execute to update local branch prediction
243 * structures */
244 updateBranchPrediction(branch_inp);
245
246 /* If a branch arrives, don't try and do anything about it. Only
247 * react to your own predictions */
248 if (branch_inp.isStreamChange()) {
249 DPRINTF(Fetch, "Dumping all input as a stream changing branch"
250 " has arrived\n");
250 dumpAllInput();
251 havePC = false;
251 dumpAllInput(branch_inp.threadId);
252 fetchInfo[branch_inp.threadId].havePC = false;
252 }
253
253 }
254
255 assert(insts_out.isBubble());
254 /* Even when blocked, clear out input lines with the wrong
255 * prediction sequence number */
256 /* Even when blocked, clear out input lines with the wrong
257 * prediction sequence number */
256 {
257 const ForwardLineData *line_in = getInput();
258 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
259 Fetch2ThreadInfo &thread = fetchInfo[tid];
258
260
261 thread.blocked = !nextStageReserve[tid].canReserve();
262
263 const ForwardLineData *line_in = getInput(tid);
264
259 while (line_in &&
265 while (line_in &&
260 expectedStreamSeqNum == line_in->id.streamSeqNum &&
261 predictionSeqNum != line_in->id.predictionSeqNum)
266 thread.expectedStreamSeqNum == line_in->id.streamSeqNum &&
267 thread.predictionSeqNum != line_in->id.predictionSeqNum)
262 {
263 DPRINTF(Fetch, "Discarding line %s"
264 " due to predictionSeqNum mismatch (expected: %d)\n",
268 {
269 DPRINTF(Fetch, "Discarding line %s"
270 " due to predictionSeqNum mismatch (expected: %d)\n",
265 line_in->id, predictionSeqNum);
271 line_in->id, thread.predictionSeqNum);
266
272
267 popInput();
268 havePC = false;
273 popInput(tid);
274 fetchInfo[tid].havePC = false;
269
270 if (processMoreThanOneInput) {
271 DPRINTF(Fetch, "Wrapping\n");
275
276 if (processMoreThanOneInput) {
277 DPRINTF(Fetch, "Wrapping\n");
272 line_in = getInput();
278 line_in = getInput(tid);
273 } else {
274 line_in = NULL;
275 }
276 }
277 }
278
279 } else {
280 line_in = NULL;
281 }
282 }
283 }
284
279 if (!nextStageReserve.canReserve()) {
280 blocked = true;
281 } else {
282 const ForwardLineData *line_in = getInput();
285 ThreadID tid = getScheduledThread();
286 DPRINTF(Fetch, "Scheduled Thread: %d\n", tid);
283
287
288 assert(insts_out.isBubble());
289 if (tid != InvalidThreadID) {
290 Fetch2ThreadInfo &fetch_info = fetchInfo[tid];
291
292 const ForwardLineData *line_in = getInput(tid);
293
284 unsigned int output_index = 0;
285
286 /* Pack instructions into the output while we can. This may involve
287 * using more than one input line. Note that lineWidth will be 0
288 * for faulting lines */
289 while (line_in &&
290 (line_in->isFault() ||
294 unsigned int output_index = 0;
295
296 /* Pack instructions into the output while we can. This may involve
297 * using more than one input line. Note that lineWidth will be 0
298 * for faulting lines */
299 while (line_in &&
300 (line_in->isFault() ||
291 inputIndex < line_in->lineWidth) && /* More input */
301 fetch_info.inputIndex < line_in->lineWidth) && /* More input */
292 output_index < outputWidth && /* More output to fill */
293 prediction.isBubble() /* No predicted branch */)
294 {
295 ThreadContext *thread = cpu.getContext(line_in->id.threadId);
296 TheISA::Decoder *decoder = thread->getDecoderPtr();
297
298 /* Discard line due to prediction sequence number being wrong but
299 * without the streamSeqNum number having changed */
300 bool discard_line =
302 output_index < outputWidth && /* More output to fill */
303 prediction.isBubble() /* No predicted branch */)
304 {
305 ThreadContext *thread = cpu.getContext(line_in->id.threadId);
306 TheISA::Decoder *decoder = thread->getDecoderPtr();
307
308 /* Discard line due to prediction sequence number being wrong but
309 * without the streamSeqNum number having changed */
310 bool discard_line =
301 expectedStreamSeqNum == line_in->id.streamSeqNum &&
302 predictionSeqNum != line_in->id.predictionSeqNum;
311 fetch_info.expectedStreamSeqNum == line_in->id.streamSeqNum &&
312 fetch_info.predictionSeqNum != line_in->id.predictionSeqNum;
303
304 /* Set the PC if the stream changes. Setting havePC to false in
305 * a previous cycle handles all other change of flow of control
306 * issues */
313
314 /* Set the PC if the stream changes. Setting havePC to false in
315 * a previous cycle handles all other change of flow of control
316 * issues */
307 bool set_pc = lastStreamSeqNum != line_in->id.streamSeqNum;
317 bool set_pc = fetch_info.lastStreamSeqNum != line_in->id.streamSeqNum;
308
318
309 if (!discard_line && (!havePC || set_pc)) {
319 if (!discard_line && (!fetch_info.havePC || set_pc)) {
310 /* Set the inputIndex to be the MachInst-aligned offset
311 * from lineBaseAddr of the new PC value */
320 /* Set the inputIndex to be the MachInst-aligned offset
321 * from lineBaseAddr of the new PC value */
312 inputIndex =
322 fetch_info.inputIndex =
313 (line_in->pc.instAddr() & BaseCPU::PCMask) -
314 line_in->lineBaseAddr;
315 DPRINTF(Fetch, "Setting new PC value: %s inputIndex: 0x%x"
316 " lineBaseAddr: 0x%x lineWidth: 0x%x\n",
323 (line_in->pc.instAddr() & BaseCPU::PCMask) -
324 line_in->lineBaseAddr;
325 DPRINTF(Fetch, "Setting new PC value: %s inputIndex: 0x%x"
326 " lineBaseAddr: 0x%x lineWidth: 0x%x\n",
317 line_in->pc, inputIndex, line_in->lineBaseAddr,
327 line_in->pc, fetch_info.inputIndex, line_in->lineBaseAddr,
318 line_in->lineWidth);
328 line_in->lineWidth);
319 pc = line_in->pc;
320 havePC = true;
329 fetch_info.pc = line_in->pc;
330 fetch_info.havePC = true;
321 decoder->reset();
322 }
323
324 /* The generated instruction. Leave as NULL if no instruction
325 * is to be packed into the output */
326 MinorDynInstPtr dyn_inst = NULL;
327
328 if (discard_line) {
329 /* Rest of line was from an older prediction in the same
330 * stream */
331 DPRINTF(Fetch, "Discarding line %s (from inputIndex: %d)"
332 " due to predictionSeqNum mismatch (expected: %d)\n",
331 decoder->reset();
332 }
333
334 /* The generated instruction. Leave as NULL if no instruction
335 * is to be packed into the output */
336 MinorDynInstPtr dyn_inst = NULL;
337
338 if (discard_line) {
339 /* Rest of line was from an older prediction in the same
340 * stream */
341 DPRINTF(Fetch, "Discarding line %s (from inputIndex: %d)"
342 " due to predictionSeqNum mismatch (expected: %d)\n",
333 line_in->id, inputIndex, predictionSeqNum);
343 line_in->id, fetch_info.inputIndex,
344 fetch_info.predictionSeqNum);
334 } else if (line_in->isFault()) {
335 /* Pack a fault as a MinorDynInst with ->fault set */
336
337 /* Make a new instruction and pick up the line, stream,
338 * prediction, thread ids from the incoming line */
339 dyn_inst = new MinorDynInst(line_in->id);
340
341 /* Fetch and prediction sequence numbers originate here */
345 } else if (line_in->isFault()) {
346 /* Pack a fault as a MinorDynInst with ->fault set */
347
348 /* Make a new instruction and pick up the line, stream,
349 * prediction, thread ids from the incoming line */
350 dyn_inst = new MinorDynInst(line_in->id);
351
352 /* Fetch and prediction sequence numbers originate here */
342 dyn_inst->id.fetchSeqNum = fetchSeqNum;
343 dyn_inst->id.predictionSeqNum = predictionSeqNum;
353 dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
354 dyn_inst->id.predictionSeqNum = fetch_info.predictionSeqNum;
344 /* To complete the set, test that exec sequence number has
345 * not been set */
346 assert(dyn_inst->id.execSeqNum == 0);
347
355 /* To complete the set, test that exec sequence number has
356 * not been set */
357 assert(dyn_inst->id.execSeqNum == 0);
358
348 dyn_inst->pc = pc;
359 dyn_inst->pc = fetch_info.pc;
349
350 /* Pack a faulting instruction but allow other
351 * instructions to be generated. (Fetch2 makes no
352 * immediate judgement about streamSeqNum) */
353 dyn_inst->fault = line_in->fault;
354 DPRINTF(Fetch, "Fault being passed output_index: "
355 "%d: %s\n", output_index, dyn_inst->fault->name());
356 } else {
357 uint8_t *line = line_in->line;
358
359 TheISA::MachInst inst_word;
360 /* The instruction is wholly in the line, can just
361 * assign */
362 inst_word = TheISA::gtoh(
363 *(reinterpret_cast<TheISA::MachInst *>
360
361 /* Pack a faulting instruction but allow other
362 * instructions to be generated. (Fetch2 makes no
363 * immediate judgement about streamSeqNum) */
364 dyn_inst->fault = line_in->fault;
365 DPRINTF(Fetch, "Fault being passed output_index: "
366 "%d: %s\n", output_index, dyn_inst->fault->name());
367 } else {
368 uint8_t *line = line_in->line;
369
370 TheISA::MachInst inst_word;
371 /* The instruction is wholly in the line, can just
372 * assign */
373 inst_word = TheISA::gtoh(
374 *(reinterpret_cast<TheISA::MachInst *>
364 (line + inputIndex)));
375 (line + fetch_info.inputIndex)));
365
366 if (!decoder->instReady()) {
376
377 if (!decoder->instReady()) {
367 decoder->moreBytes(pc,
368 line_in->lineBaseAddr + inputIndex, inst_word);
369 DPRINTF(Fetch, "Offering MachInst to decoder"
370 " addr: 0x%x\n", line_in->lineBaseAddr + inputIndex);
378 decoder->moreBytes(fetch_info.pc,
379 line_in->lineBaseAddr + fetch_info.inputIndex,
380 inst_word);
381 DPRINTF(Fetch, "Offering MachInst to decoder addr: 0x%x\n",
382 line_in->lineBaseAddr + fetch_info.inputIndex);
371 }
372
373 /* Maybe make the above a loop to accomodate ISAs with
374 * instructions longer than sizeof(MachInst) */
375
376 if (decoder->instReady()) {
377 /* Make a new instruction and pick up the line, stream,
378 * prediction, thread ids from the incoming line */
379 dyn_inst = new MinorDynInst(line_in->id);
380
381 /* Fetch and prediction sequence numbers originate here */
383 }
384
385 /* Maybe make the above a loop to accomodate ISAs with
386 * instructions longer than sizeof(MachInst) */
387
388 if (decoder->instReady()) {
389 /* Make a new instruction and pick up the line, stream,
390 * prediction, thread ids from the incoming line */
391 dyn_inst = new MinorDynInst(line_in->id);
392
393 /* Fetch and prediction sequence numbers originate here */
382 dyn_inst->id.fetchSeqNum = fetchSeqNum;
383 dyn_inst->id.predictionSeqNum = predictionSeqNum;
394 dyn_inst->id.fetchSeqNum = fetch_info.fetchSeqNum;
395 dyn_inst->id.predictionSeqNum = fetch_info.predictionSeqNum;
384 /* To complete the set, test that exec sequence number
385 * has not been set */
386 assert(dyn_inst->id.execSeqNum == 0);
387
388 /* Note that the decoder can update the given PC.
389 * Remember not to assign it until *after* calling
390 * decode */
396 /* To complete the set, test that exec sequence number
397 * has not been set */
398 assert(dyn_inst->id.execSeqNum == 0);
399
400 /* Note that the decoder can update the given PC.
401 * Remember not to assign it until *after* calling
402 * decode */
391 StaticInstPtr decoded_inst = decoder->decode(pc);
403 StaticInstPtr decoded_inst = decoder->decode(fetch_info.pc);
392 dyn_inst->staticInst = decoded_inst;
393
404 dyn_inst->staticInst = decoded_inst;
405
394 dyn_inst->pc = pc;
406 dyn_inst->pc = fetch_info.pc;
407 DPRINTF(Fetch, "decoder inst %s\n", *dyn_inst);
395
408
409
396 DPRINTF(Fetch, "Instruction extracted from line %s"
397 " lineWidth: %d output_index: %d inputIndex: %d"
398 " pc: %s inst: %s\n",
399 line_in->id,
410 DPRINTF(Fetch, "Instruction extracted from line %s"
411 " lineWidth: %d output_index: %d inputIndex: %d"
412 " pc: %s inst: %s\n",
413 line_in->id,
400 line_in->lineWidth, output_index, inputIndex,
401 pc, *dyn_inst);
414 line_in->lineWidth, output_index, fetch_info.inputIndex,
415 fetch_info.pc, *dyn_inst);
402
403#if THE_ISA == X86_ISA || THE_ISA == ARM_ISA
404 /* In SE mode, it's possible to branch to a microop when
405 * replaying faults such as page faults (or simply
406 * intra-microcode branches in X86). Unfortunately,
407 * as Minor has micro-op decomposition in a separate
408 * pipeline stage from instruction decomposition, the
409 * following advancePC (which may follow a branch with
410 * microPC() != 0) *must* see a fresh macroop. This
411 * kludge should be improved with an addition to PCState
412 * but I offer it in this form for the moment
413 *
414 * X86 can branch within microops so we need to deal with
415 * the case that, after a branch, the first un-advanced PC
416 * may be pointing to a microop other than 0. Once
417 * advanced, however, the microop number *must* be 0 */
416
417#if THE_ISA == X86_ISA || THE_ISA == ARM_ISA
418 /* In SE mode, it's possible to branch to a microop when
419 * replaying faults such as page faults (or simply
420 * intra-microcode branches in X86). Unfortunately,
421 * as Minor has micro-op decomposition in a separate
422 * pipeline stage from instruction decomposition, the
423 * following advancePC (which may follow a branch with
424 * microPC() != 0) *must* see a fresh macroop. This
425 * kludge should be improved with an addition to PCState
426 * but I offer it in this form for the moment
427 *
428 * X86 can branch within microops so we need to deal with
429 * the case that, after a branch, the first un-advanced PC
430 * may be pointing to a microop other than 0. Once
431 * advanced, however, the microop number *must* be 0 */
418 pc.upc(0);
419 pc.nupc(1);
432 fetch_info.pc.upc(0);
433 fetch_info.pc.nupc(1);
420#endif
421
422 /* Advance PC for the next instruction */
434#endif
435
436 /* Advance PC for the next instruction */
423 TheISA::advancePC(pc, decoded_inst);
437 TheISA::advancePC(fetch_info.pc, decoded_inst);
424
425 /* Predict any branches and issue a branch if
426 * necessary */
427 predictBranch(dyn_inst, prediction);
428 } else {
429 DPRINTF(Fetch, "Inst not ready yet\n");
430 }
431
432 /* Step on the pointer into the line if there's no
433 * complete instruction waiting */
434 if (decoder->needMoreBytes()) {
438
439 /* Predict any branches and issue a branch if
440 * necessary */
441 predictBranch(dyn_inst, prediction);
442 } else {
443 DPRINTF(Fetch, "Inst not ready yet\n");
444 }
445
446 /* Step on the pointer into the line if there's no
447 * complete instruction waiting */
448 if (decoder->needMoreBytes()) {
435 inputIndex += sizeof(TheISA::MachInst);
449 fetch_info.inputIndex += sizeof(TheISA::MachInst);
436
437 DPRINTF(Fetch, "Updated inputIndex value PC: %s"
438 " inputIndex: 0x%x lineBaseAddr: 0x%x lineWidth: 0x%x\n",
450
451 DPRINTF(Fetch, "Updated inputIndex value PC: %s"
452 " inputIndex: 0x%x lineBaseAddr: 0x%x lineWidth: 0x%x\n",
439 line_in->pc, inputIndex, line_in->lineBaseAddr,
453 line_in->pc, fetch_info.inputIndex, line_in->lineBaseAddr,
440 line_in->lineWidth);
441 }
442 }
443
444 if (dyn_inst) {
445 /* Step to next sequence number */
454 line_in->lineWidth);
455 }
456 }
457
458 if (dyn_inst) {
459 /* Step to next sequence number */
446 fetchSeqNum++;
460 fetch_info.fetchSeqNum++;
447
448 /* Correctly size the output before writing */
461
462 /* Correctly size the output before writing */
449 if (output_index == 0)
463 if (output_index == 0) {
450 insts_out.resize(outputWidth);
464 insts_out.resize(outputWidth);
465 }
451 /* Pack the generated dynamic instruction into the output */
452 insts_out.insts[output_index] = dyn_inst;
453 output_index++;
454
455 /* Output MinorTrace instruction info for
456 * pre-microop decomposition macroops */
457 if (DTRACE(MinorTrace) && !dyn_inst->isFault() &&
458 dyn_inst->staticInst->isMacroop())
459 {
460 dyn_inst->minorTraceInst(*this);
461 }
462 }
463
464 /* Remember the streamSeqNum of this line so we can tell when
465 * we change stream */
466 /* Pack the generated dynamic instruction into the output */
467 insts_out.insts[output_index] = dyn_inst;
468 output_index++;
469
470 /* Output MinorTrace instruction info for
471 * pre-microop decomposition macroops */
472 if (DTRACE(MinorTrace) && !dyn_inst->isFault() &&
473 dyn_inst->staticInst->isMacroop())
474 {
475 dyn_inst->minorTraceInst(*this);
476 }
477 }
478
479 /* Remember the streamSeqNum of this line so we can tell when
480 * we change stream */
466 lastStreamSeqNum = line_in->id.streamSeqNum;
481 fetch_info.lastStreamSeqNum = line_in->id.streamSeqNum;
467
468 /* Asked to discard line or there was a branch or fault */
469 if (!prediction.isBubble() || /* The remains of a
470 line with a prediction in it */
471 line_in->isFault() /* A line which is just a fault */)
472 {
473 DPRINTF(Fetch, "Discarding all input on branch/fault\n");
482
483 /* Asked to discard line or there was a branch or fault */
484 if (!prediction.isBubble() || /* The remains of a
485 line with a prediction in it */
486 line_in->isFault() /* A line which is just a fault */)
487 {
488 DPRINTF(Fetch, "Discarding all input on branch/fault\n");
474 dumpAllInput();
475 havePC = false;
489 dumpAllInput(tid);
490 fetch_info.havePC = false;
476 line_in = NULL;
477 } else if (discard_line) {
478 /* Just discard one line, one's behind it may have new
479 * stream sequence numbers. There's a DPRINTF above
480 * for this event */
491 line_in = NULL;
492 } else if (discard_line) {
493 /* Just discard one line, one's behind it may have new
494 * stream sequence numbers. There's a DPRINTF above
495 * for this event */
481 popInput();
482 havePC = false;
496 popInput(tid);
497 fetch_info.havePC = false;
483 line_in = NULL;
498 line_in = NULL;
484 } else if (inputIndex == line_in->lineWidth) {
499 } else if (fetch_info.inputIndex == line_in->lineWidth) {
485 /* Got to end of a line, pop the line but keep PC
486 * in case this is a line-wrapping inst. */
500 /* Got to end of a line, pop the line but keep PC
501 * in case this is a line-wrapping inst. */
487 popInput();
502 popInput(tid);
488 line_in = NULL;
489 }
490
491 if (!line_in && processMoreThanOneInput) {
492 DPRINTF(Fetch, "Wrapping\n");
503 line_in = NULL;
504 }
505
506 if (!line_in && processMoreThanOneInput) {
507 DPRINTF(Fetch, "Wrapping\n");
493 line_in = getInput();
508 line_in = getInput(tid);
494 }
495 }
496
497 /* The rest of the output (if any) should already have been packed
498 * with bubble instructions by insts_out's initialisation */
499 }
509 }
510 }
511
512 /* The rest of the output (if any) should already have been packed
513 * with bubble instructions by insts_out's initialisation */
514 }
500
515 if (tid == InvalidThreadID) {
516 assert(insts_out.isBubble());
517 }
501 /** Reserve a slot in the next stage and output data */
502 *predictionOut.inputWire = prediction;
503
504 /* If we generated output, reserve space for the result in the next stage
505 * and mark the stage as being active this cycle */
506 if (!insts_out.isBubble()) {
507 /* Note activity of following buffer */
508 cpu.activityRecorder->activity();
518 /** Reserve a slot in the next stage and output data */
519 *predictionOut.inputWire = prediction;
520
521 /* If we generated output, reserve space for the result in the next stage
522 * and mark the stage as being active this cycle */
523 if (!insts_out.isBubble()) {
524 /* Note activity of following buffer */
525 cpu.activityRecorder->activity();
509 nextStageReserve.reserve();
526 insts_out.threadId = tid;
527 nextStageReserve[tid].reserve();
510 }
511
512 /* If we still have input to process and somewhere to put it,
513 * mark stage as active */
528 }
529
530 /* If we still have input to process and somewhere to put it,
531 * mark stage as active */
514 if (getInput() && nextStageReserve.canReserve())
515 cpu.activityRecorder->activateStage(Pipeline::Fetch2StageId);
532 for (ThreadID i = 0; i < cpu.numThreads; i++)
533 {
534 if (getInput(i) && nextStageReserve[i].canReserve()) {
535 cpu.activityRecorder->activateStage(Pipeline::Fetch2StageId);
536 break;
537 }
538 }
516
517 /* Make sure the input (if any left) is pushed */
539
540 /* Make sure the input (if any left) is pushed */
518 inputBuffer.pushTail();
541 if (!inp.outputWire->isBubble())
542 inputBuffer[inp.outputWire->id.threadId].pushTail();
519}
520
543}
544
545inline ThreadID
546Fetch2::getScheduledThread()
547{
548 /* Select thread via policy. */
549 std::vector<ThreadID> priority_list;
550
551 switch (cpu.threadPolicy) {
552 case Enums::SingleThreaded:
553 priority_list.push_back(0);
554 break;
555 case Enums::RoundRobin:
556 priority_list = cpu.roundRobinPriority(threadPriority);
557 break;
558 case Enums::Random:
559 priority_list = cpu.randomPriority();
560 break;
561 default:
562 panic("Unknown fetch policy");
563 }
564
565 for (auto tid : priority_list) {
566 if (cpu.getContext(tid)->status() == ThreadContext::Active &&
567 getInput(tid) && !fetchInfo[tid].blocked) {
568 threadPriority = tid;
569 return tid;
570 }
571 }
572
573 return InvalidThreadID;
574}
575
521bool
522Fetch2::isDrained()
523{
576bool
577Fetch2::isDrained()
578{
524 return inputBuffer.empty() &&
525 (*inp.outputWire).isBubble() &&
526 (*predictionOut.inputWire).isBubble();
579 for (const auto &buffer : inputBuffer) {
580 if (!buffer.empty())
581 return false;
582 }
583
584 return (*inp.outputWire).isBubble() &&
585 (*predictionOut.inputWire).isBubble();
527}
528
529void
530Fetch2::minorTrace() const
531{
532 std::ostringstream data;
533
586}
587
588void
589Fetch2::minorTrace() const
590{
591 std::ostringstream data;
592
534 if (blocked)
593 if (fetchInfo[0].blocked)
535 data << 'B';
536 else
537 (*out.inputWire).reportData(data);
538
539 MINORTRACE("inputIndex=%d havePC=%d predictionSeqNum=%d insts=%s\n",
594 data << 'B';
595 else
596 (*out.inputWire).reportData(data);
597
598 MINORTRACE("inputIndex=%d havePC=%d predictionSeqNum=%d insts=%s\n",
540 inputIndex, havePC, predictionSeqNum, data.str());
541 inputBuffer.minorTrace();
599 fetchInfo[0].inputIndex, fetchInfo[0].havePC, fetchInfo[0].predictionSeqNum, data.str());
600 inputBuffer[0].minorTrace();
542}
543
544}
601}
602
603}