fetch1.hh (11567:560d7fbbddd1) fetch1.hh (12749:223c83ed9979)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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125
126 /** FetchRequests carry packets while they're in the requests and
127 * transfers responses queues. When a Packet returns from the memory
128 * system, its request needs to have its packet updated as this may
129 * have changed in flight */
130 PacketPtr packet;
131
132 /** The underlying request that this fetch represents */
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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125
126 /** FetchRequests carry packets while they're in the requests and
127 * transfers responses queues. When a Packet returns from the memory
128 * system, its request needs to have its packet updated as this may
129 * have changed in flight */
130 PacketPtr packet;
131
132 /** The underlying request that this fetch represents */
133 Request request;
133 RequestPtr request;
134
135 /** PC to fixup with line address */
136 TheISA::PCState pc;
137
138 /** Fill in a fault if one happens during fetch, check this by
139 * picking apart the response packet */
140 Fault fault;
141

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158
159 /** Interface for ITLB responses. We can handle delay, so don't
160 * do anything */
161 void markDelayed() { }
162
163 /** Interface for ITLB responses. Populates self and then passes
164 * the request on to the ports' handleTLBResponse member
165 * function */
134
135 /** PC to fixup with line address */
136 TheISA::PCState pc;
137
138 /** Fill in a fault if one happens during fetch, check this by
139 * picking apart the response packet */
140 Fault fault;
141

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158
159 /** Interface for ITLB responses. We can handle delay, so don't
160 * do anything */
161 void markDelayed() { }
162
163 /** Interface for ITLB responses. Populates self and then passes
164 * the request on to the ports' handleTLBResponse member
165 * function */
166 void finish(const Fault &fault_, RequestPtr request_,
166 void finish(const Fault &fault_, const RequestPtr &request_,
167 ThreadContext *tc, BaseTLB::Mode mode);
168
169 public:
170 FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
171 SenderState(),
172 fetch(fetch_),
173 state(NotIssued),
174 id(id_),
175 packet(NULL),
176 request(),
177 pc(pc_),
178 fault(NoFault)
167 ThreadContext *tc, BaseTLB::Mode mode);
168
169 public:
170 FetchRequest(Fetch1 &fetch_, InstId id_, TheISA::PCState pc_) :
171 SenderState(),
172 fetch(fetch_),
173 state(NotIssued),
174 id(id_),
175 packet(NULL),
176 request(),
177 pc(pc_),
178 fault(NoFault)
179 { }
179 {
180 request = std::make_shared<Request>();
181 }
180
181 ~FetchRequest();
182 };
183
184 typedef FetchRequest *FetchRequestPtr;
185
186 protected:
187 /** Construction-assigned data members */

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183 ~FetchRequest();
184 };
185
186 typedef FetchRequest *FetchRequestPtr;
187
188 protected:
189 /** Construction-assigned data members */

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