| fetch1.hh (10537:47fe87b0cf97) | fetch1.hh (10713:eddb533708cb) |
|---|---|
| 1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72 IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) : 73 MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_) 74 { } 75 76 protected: 77 bool recvTimingResp(PacketPtr pkt) 78 { return fetch.recvTimingResp(pkt); } 79 | 1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 63 unchanged lines hidden (view full) --- 72 IcachePort(std::string name, Fetch1 &fetch_, MinorCPU &cpu) : 73 MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_) 74 { } 75 76 protected: 77 bool recvTimingResp(PacketPtr pkt) 78 { return fetch.recvTimingResp(pkt); } 79 |
| 80 void recvRetry() { fetch.recvRetry(); } | 80 void recvReqRetry() { fetch.recvReqRetry(); } |
| 81 }; 82 83 /** Memory access queuing. 84 * 85 * A request can be submitted by pushing it onto the requests queue after 86 * issuing an ITLB lookup (state becomes InTranslation) with a 87 * FetchSenderState senderState containing the current lineSeqNum and 88 * stream/predictionSeqNum. --- 251 unchanged lines hidden (view full) --- 340 unsigned int numInFlightFetches(); 341 342 /** Print the appropriate MinorLine line for a fetch response */ 343 void minorTraceResponseLine(const std::string &name, 344 FetchRequestPtr response) const; 345 346 /** Memory interface */ 347 virtual bool recvTimingResp(PacketPtr pkt); | 81 }; 82 83 /** Memory access queuing. 84 * 85 * A request can be submitted by pushing it onto the requests queue after 86 * issuing an ITLB lookup (state becomes InTranslation) with a 87 * FetchSenderState senderState containing the current lineSeqNum and 88 * stream/predictionSeqNum. --- 251 unchanged lines hidden (view full) --- 340 unsigned int numInFlightFetches(); 341 342 /** Print the appropriate MinorLine line for a fetch response */ 343 void minorTraceResponseLine(const std::string &name, 344 FetchRequestPtr response) const; 345 346 /** Memory interface */ 347 virtual bool recvTimingResp(PacketPtr pkt); |
| 348 virtual void recvRetry(); | 348 virtual void recvReqRetry(); |
| 349 350 public: 351 Fetch1(const std::string &name_, 352 MinorCPU &cpu_, 353 MinorCPUParams ¶ms, 354 Latch<BranchData>::Output inp_, 355 Latch<ForwardLineData>::Input out_, 356 Latch<BranchData>::Output prediction_, --- 19 unchanged lines hidden --- | 349 350 public: 351 Fetch1(const std::string &name_, 352 MinorCPU &cpu_, 353 MinorCPUParams ¶ms, 354 Latch<BranchData>::Output inp_, 355 Latch<ForwardLineData>::Input out_, 356 Latch<BranchData>::Output prediction_, --- 19 unchanged lines hidden --- |