fetch1.cc (10259:ebb376f73dd2) fetch1.cc (10379:c00f6d7e2681)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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199 packet->allocate();
200
201 /* This FetchRequest becomes SenderState to allow the response to be
202 * identified */
203 packet->pushSenderState(this);
204}
205
206void
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 190 unchanged lines hidden (view full) ---

199 packet->allocate();
200
201 /* This FetchRequest becomes SenderState to allow the response to be
202 * identified */
203 packet->pushSenderState(this);
204}
205
206void
207Fetch1::FetchRequest::finish(
208 Fault fault_, RequestPtr request_, ThreadContext *tc, BaseTLB::Mode mode)
207Fetch1::FetchRequest::finish(const Fault &fault_, RequestPtr request_,
208 ThreadContext *tc, BaseTLB::Mode mode)
209{
210 fault = fault_;
211
212 state = Translated;
213 fetch.handleTLBResponse(this);
214
215 /* Let's try and wake up the processor for the next cycle */
216 fetch.cpu.wakeupOnEvent(Pipeline::Fetch1StageId);

--- 460 unchanged lines hidden --- 		209{
210 fault = fault_;
211
212 state = Translated;
213 fetch.handleTLBResponse(this);
214
215 /* Let's try and wake up the processor for the next cycle */
216 fetch.cpu.wakeupOnEvent(Pipeline::Fetch1StageId);

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