1/* 2 * Copyright (c) 2013-2014,2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 1669 unchanged lines hidden (view full) --- 1678 priority_list = cpu.randomPriority(); 1679 break; 1680 default: 1681 panic("Invalid thread policy"); 1682 } 1683 1684 for (auto tid : priority_list) { 1685 ExecuteThreadInfo &ex_info = executeInfo[tid]; |
1686 bool can_commit_insts = !ex_info.inFlightInsts->empty(); |
1687 if (can_commit_insts) { 1688 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front()); 1689 MinorDynInstPtr inst = head_inflight_inst->inst; 1690 1691 can_commit_insts = can_commit_insts && 1692 (!inst->inLSQ || (lsq.findResponse(inst) != NULL)); 1693 1694 if (!inst->inLSQ) { --- 49 unchanged lines hidden (view full) --- 1744 case Enums::Random: 1745 priority_list = cpu.randomPriority(); 1746 break; 1747 default: 1748 panic("Invalid thread scheduling policy."); 1749 } 1750 1751 for (auto tid : priority_list) { |
1752 if (getInput(tid)) { |
1753 issuePriority = tid; 1754 return tid; 1755 } 1756 } 1757 1758 return InvalidThreadID; 1759} 1760 --- 115 unchanged lines hidden --- |