1/*
2 * Copyright (c) 2013-2014,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/execute.hh"
41
42#include "arch/locked_mem.hh"
43#include "arch/registers.hh"
44#include "arch/utility.hh"
45#include "cpu/minor/cpu.hh"
46#include "cpu/minor/exec_context.hh"
47#include "cpu/minor/fetch1.hh"
48#include "cpu/minor/lsq.hh"
49#include "cpu/op_class.hh"
50#include "debug/Activity.hh"
51#include "debug/Branch.hh"
52#include "debug/Drain.hh"
53#include "debug/MinorExecute.hh"
54#include "debug/MinorInterrupt.hh"
55#include "debug/MinorMem.hh"
56#include "debug/MinorTrace.hh"
57#include "debug/PCEvent.hh"
58
59namespace Minor
60{
61
62Execute::Execute(const std::string &name_,
63 MinorCPU &cpu_,
64 MinorCPUParams ¶ms,
65 Latch<ForwardInstData>::Output inp_,
66 Latch<BranchData>::Input out_) :
67 Named(name_),
68 inp(inp_),
69 out(out_),
70 cpu(cpu_),
71 issueLimit(params.executeIssueLimit),
72 memoryIssueLimit(params.executeMemoryIssueLimit),
73 commitLimit(params.executeCommitLimit),
74 memoryCommitLimit(params.executeMemoryCommitLimit),
75 processMoreThanOneInput(params.executeCycleInput),
76 fuDescriptions(*params.executeFuncUnits),
77 numFuncUnits(fuDescriptions.funcUnits.size()),
78 setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit),
79 setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue),
80 allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue),
81 noCostFUIndex(fuDescriptions.funcUnits.size() + 1),
82 lsq(name_ + ".lsq", name_ + ".dcache_port",
83 cpu_, *this,
84 params.executeMaxAccessesInMemory,
85 params.executeMemoryWidth,
86 params.executeLSQRequestsQueueSize,
87 params.executeLSQTransfersQueueSize,
88 params.executeLSQStoreBufferSize,
89 params.executeLSQMaxStoreBufferStoresPerCycle),
90 executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)),
91 interruptPriority(0),
92 issuePriority(0),
93 commitPriority(0)
94{
95 if (commitLimit < 1) {
96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
97 commitLimit);
98 }
99
100 if (issueLimit < 1) {
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
102 issueLimit);
103 }
104
105 if (memoryIssueLimit < 1) {
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_,
107 memoryIssueLimit);
108 }
109
110 if (memoryCommitLimit > commitLimit) {
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
112 " executeCommitLimit (%d)\n",
113 name_, memoryCommitLimit, commitLimit);
114 }
115
116 if (params.executeInputBufferSize < 1) {
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
118 params.executeInputBufferSize);
119 }
120
121 if (params.executeInputBufferSize < 1) {
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
123 params.executeInputBufferSize);
124 }
125
126 /* This should be large enough to count all the in-FU instructions
127 * which need to be accounted for in the inFlightInsts
128 * queue */
129 unsigned int total_slots = 0;
130
131 /* Make FUPipelines for each MinorFU */
132 for (unsigned int i = 0; i < numFuncUnits; i++) {
133 std::ostringstream fu_name;
134 MinorFU *fu_description = fuDescriptions.funcUnits[i];
135
136 /* Note the total number of instruction slots (for sizing
137 * the inFlightInst queue) and the maximum latency of any FU
138 * (for sizing the activity recorder) */
139 total_slots += fu_description->opLat;
140
141 fu_name << name_ << ".fu." << i;
142
143 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu);
144
145 funcUnits.push_back(fu);
146 }
147
148 /** Check that there is a functional unit for all operation classes */
149 for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) {
150 bool found_fu = false;
151 unsigned int fu_index = 0;
152
153 while (fu_index < numFuncUnits && !found_fu)
154 {
155 if (funcUnits[fu_index]->provides(
156 static_cast<OpClass>(op_class)))
157 {
158 found_fu = true;
159 }
160 fu_index++;
161 }
162
163 if (!found_fu) {
164 warn("No functional unit for OpClass %s\n",
165 Enums::OpClassStrings[op_class]);
166 }
167 }
168
169 /* Per-thread structures */
170 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
171 std::string tid_str = std::to_string(tid);
172
173 /* Input Buffers */
174 inputBuffer.push_back(
175 InputBuffer<ForwardInstData>(
176 name_ + ".inputBuffer" + tid_str, "insts",
177 params.executeInputBufferSize));
178
179 /* Scoreboards */
180 scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
181
182 /* In-flight instruction records */
183 executeInfo[tid].inFlightInsts = new Queue<QueuedInst,
184 ReportTraitsAdaptor<QueuedInst> >(
185 name_ + ".inFlightInsts" + tid_str, "insts", total_slots);
186
187 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst,
188 ReportTraitsAdaptor<QueuedInst> >(
189 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots);
190 }
191}
192
193const ForwardInstData *
194Execute::getInput(ThreadID tid)
195{
196 /* Get a line from the inputBuffer to work with */
197 if (!inputBuffer[tid].empty()) {
198 const ForwardInstData &head = inputBuffer[tid].front();
199
200 return (head.isBubble() ? NULL : &(inputBuffer[tid].front()));
201 } else {
202 return NULL;
203 }
204}
205
206void
207Execute::popInput(ThreadID tid)
208{
209 if (!inputBuffer[tid].empty())
210 inputBuffer[tid].pop();
211
212 executeInfo[tid].inputIndex = 0;
213}
214
215void
216Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
217{
218 ThreadContext *thread = cpu.getContext(inst->id.threadId);
219 const TheISA::PCState &pc_before = inst->pc;
220 TheISA::PCState target = thread->pcState();
221
222 /* Force a branch for SerializeAfter/SquashAfter instructions
223 * at the end of micro-op sequence when we're not suspended */
224 bool force_branch = thread->status() != ThreadContext::Suspended &&
225 !inst->isFault() &&
226 inst->isLastOpInInst() &&
227 (inst->staticInst->isSerializeAfter() ||
228 inst->staticInst->isSquashAfter() ||
229 inst->staticInst->isIprAccess());
230
231 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
232 pc_before, target, (force_branch ? " (forcing)" : ""));
233
234 /* Will we change the PC to something other than the next instruction? */
235 bool must_branch = pc_before != target ||
236 fault != NoFault ||
237 force_branch;
238
239 /* The reason for the branch data we're about to generate, set below */
240 BranchData::Reason reason = BranchData::NoBranch;
241
242 if (fault == NoFault)
243 {
244 TheISA::advancePC(target, inst->staticInst);
245 thread->pcState(target);
246
247 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n",
248 pc_before, target);
249 }
250
| 1/*
2 * Copyright (c) 2013-2014,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/execute.hh"
41
42#include "arch/locked_mem.hh"
43#include "arch/registers.hh"
44#include "arch/utility.hh"
45#include "cpu/minor/cpu.hh"
46#include "cpu/minor/exec_context.hh"
47#include "cpu/minor/fetch1.hh"
48#include "cpu/minor/lsq.hh"
49#include "cpu/op_class.hh"
50#include "debug/Activity.hh"
51#include "debug/Branch.hh"
52#include "debug/Drain.hh"
53#include "debug/MinorExecute.hh"
54#include "debug/MinorInterrupt.hh"
55#include "debug/MinorMem.hh"
56#include "debug/MinorTrace.hh"
57#include "debug/PCEvent.hh"
58
59namespace Minor
60{
61
62Execute::Execute(const std::string &name_,
63 MinorCPU &cpu_,
64 MinorCPUParams ¶ms,
65 Latch<ForwardInstData>::Output inp_,
66 Latch<BranchData>::Input out_) :
67 Named(name_),
68 inp(inp_),
69 out(out_),
70 cpu(cpu_),
71 issueLimit(params.executeIssueLimit),
72 memoryIssueLimit(params.executeMemoryIssueLimit),
73 commitLimit(params.executeCommitLimit),
74 memoryCommitLimit(params.executeMemoryCommitLimit),
75 processMoreThanOneInput(params.executeCycleInput),
76 fuDescriptions(*params.executeFuncUnits),
77 numFuncUnits(fuDescriptions.funcUnits.size()),
78 setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit),
79 setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue),
80 allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue),
81 noCostFUIndex(fuDescriptions.funcUnits.size() + 1),
82 lsq(name_ + ".lsq", name_ + ".dcache_port",
83 cpu_, *this,
84 params.executeMaxAccessesInMemory,
85 params.executeMemoryWidth,
86 params.executeLSQRequestsQueueSize,
87 params.executeLSQTransfersQueueSize,
88 params.executeLSQStoreBufferSize,
89 params.executeLSQMaxStoreBufferStoresPerCycle),
90 executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)),
91 interruptPriority(0),
92 issuePriority(0),
93 commitPriority(0)
94{
95 if (commitLimit < 1) {
96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
97 commitLimit);
98 }
99
100 if (issueLimit < 1) {
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
102 issueLimit);
103 }
104
105 if (memoryIssueLimit < 1) {
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_,
107 memoryIssueLimit);
108 }
109
110 if (memoryCommitLimit > commitLimit) {
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
112 " executeCommitLimit (%d)\n",
113 name_, memoryCommitLimit, commitLimit);
114 }
115
116 if (params.executeInputBufferSize < 1) {
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
118 params.executeInputBufferSize);
119 }
120
121 if (params.executeInputBufferSize < 1) {
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
123 params.executeInputBufferSize);
124 }
125
126 /* This should be large enough to count all the in-FU instructions
127 * which need to be accounted for in the inFlightInsts
128 * queue */
129 unsigned int total_slots = 0;
130
131 /* Make FUPipelines for each MinorFU */
132 for (unsigned int i = 0; i < numFuncUnits; i++) {
133 std::ostringstream fu_name;
134 MinorFU *fu_description = fuDescriptions.funcUnits[i];
135
136 /* Note the total number of instruction slots (for sizing
137 * the inFlightInst queue) and the maximum latency of any FU
138 * (for sizing the activity recorder) */
139 total_slots += fu_description->opLat;
140
141 fu_name << name_ << ".fu." << i;
142
143 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu);
144
145 funcUnits.push_back(fu);
146 }
147
148 /** Check that there is a functional unit for all operation classes */
149 for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) {
150 bool found_fu = false;
151 unsigned int fu_index = 0;
152
153 while (fu_index < numFuncUnits && !found_fu)
154 {
155 if (funcUnits[fu_index]->provides(
156 static_cast<OpClass>(op_class)))
157 {
158 found_fu = true;
159 }
160 fu_index++;
161 }
162
163 if (!found_fu) {
164 warn("No functional unit for OpClass %s\n",
165 Enums::OpClassStrings[op_class]);
166 }
167 }
168
169 /* Per-thread structures */
170 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
171 std::string tid_str = std::to_string(tid);
172
173 /* Input Buffers */
174 inputBuffer.push_back(
175 InputBuffer<ForwardInstData>(
176 name_ + ".inputBuffer" + tid_str, "insts",
177 params.executeInputBufferSize));
178
179 /* Scoreboards */
180 scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
181
182 /* In-flight instruction records */
183 executeInfo[tid].inFlightInsts = new Queue<QueuedInst,
184 ReportTraitsAdaptor<QueuedInst> >(
185 name_ + ".inFlightInsts" + tid_str, "insts", total_slots);
186
187 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst,
188 ReportTraitsAdaptor<QueuedInst> >(
189 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots);
190 }
191}
192
193const ForwardInstData *
194Execute::getInput(ThreadID tid)
195{
196 /* Get a line from the inputBuffer to work with */
197 if (!inputBuffer[tid].empty()) {
198 const ForwardInstData &head = inputBuffer[tid].front();
199
200 return (head.isBubble() ? NULL : &(inputBuffer[tid].front()));
201 } else {
202 return NULL;
203 }
204}
205
206void
207Execute::popInput(ThreadID tid)
208{
209 if (!inputBuffer[tid].empty())
210 inputBuffer[tid].pop();
211
212 executeInfo[tid].inputIndex = 0;
213}
214
215void
216Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
217{
218 ThreadContext *thread = cpu.getContext(inst->id.threadId);
219 const TheISA::PCState &pc_before = inst->pc;
220 TheISA::PCState target = thread->pcState();
221
222 /* Force a branch for SerializeAfter/SquashAfter instructions
223 * at the end of micro-op sequence when we're not suspended */
224 bool force_branch = thread->status() != ThreadContext::Suspended &&
225 !inst->isFault() &&
226 inst->isLastOpInInst() &&
227 (inst->staticInst->isSerializeAfter() ||
228 inst->staticInst->isSquashAfter() ||
229 inst->staticInst->isIprAccess());
230
231 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
232 pc_before, target, (force_branch ? " (forcing)" : ""));
233
234 /* Will we change the PC to something other than the next instruction? */
235 bool must_branch = pc_before != target ||
236 fault != NoFault ||
237 force_branch;
238
239 /* The reason for the branch data we're about to generate, set below */
240 BranchData::Reason reason = BranchData::NoBranch;
241
242 if (fault == NoFault)
243 {
244 TheISA::advancePC(target, inst->staticInst);
245 thread->pcState(target);
246
247 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n",
248 pc_before, target);
249 }
250
|
251 if (thread->status() == ThreadContext::Suspended) {
252 /* Thread got suspended */
253 DPRINTF(Branch, "Thread got suspended: branch from 0x%x to 0x%x "
254 "inst: %s\n",
255 inst->pc.instAddr(), target.instAddr(), *inst);
256
257 reason = BranchData::SuspendThread;
258 } else if (inst->predictedTaken && !force_branch) {
| 251 if (inst->predictedTaken && !force_branch) {
|
259 /* Predicted to branch */
260 if (!must_branch) {
261 /* No branch was taken, change stream to get us back to the
262 * intended PC value */
263 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but"
264 " none happened inst: %s\n",
265 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
266
267 reason = BranchData::BadlyPredictedBranch;
268 } else if (inst->predictedTarget == target) {
269 /* Branch prediction got the right target, kill the branch and
270 * carry on.
271 * Note that this information to the branch predictor might get
272 * overwritten by a "real" branch during this cycle */
273 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly"
274 " inst: %s\n",
275 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
276
277 reason = BranchData::CorrectlyPredictedBranch;
278 } else {
279 /* Branch prediction got the wrong target */
280 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x"
281 " but got the wrong target (actual: 0x%x) inst: %s\n",
282 inst->pc.instAddr(), inst->predictedTarget.instAddr(),
283 target.instAddr(), *inst);
284
285 reason = BranchData::BadlyPredictedBranchTarget;
286 }
287 } else if (must_branch) {
288 /* Unpredicted branch */
289 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
290 inst->pc.instAddr(), target.instAddr(), *inst);
291
292 reason = BranchData::UnpredictedBranch;
293 } else {
294 /* No branch at all */
295 reason = BranchData::NoBranch;
296 }
297
298 updateBranchData(inst->id.threadId, reason, inst, target, branch);
299}
300
301void
302Execute::updateBranchData(
303 ThreadID tid,
304 BranchData::Reason reason,
305 MinorDynInstPtr inst, const TheISA::PCState &target,
306 BranchData &branch)
307{
308 if (reason != BranchData::NoBranch) {
309 /* Bump up the stream sequence number on a real branch*/
310 if (BranchData::isStreamChange(reason))
311 executeInfo[tid].streamSeqNum++;
312
313 /* Branches (even mis-predictions) don't change the predictionSeqNum,
314 * just the streamSeqNum */
315 branch = BranchData(reason, tid,
316 executeInfo[tid].streamSeqNum,
317 /* Maintaining predictionSeqNum if there's no inst is just a
318 * courtesy and looks better on minorview */
319 (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum
320 : inst->id.predictionSeqNum),
321 target, inst);
322
323 DPRINTF(Branch, "Branch data signalled: %s\n", branch);
324 }
325}
326
327void
328Execute::handleMemResponse(MinorDynInstPtr inst,
329 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
330{
331 ThreadID thread_id = inst->id.threadId;
332 ThreadContext *thread = cpu.getContext(thread_id);
333
334 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
335
336 PacketPtr packet = response->packet;
337
338 bool is_load = inst->staticInst->isLoad();
339 bool is_store = inst->staticInst->isStore();
340 bool is_atomic = inst->staticInst->isAtomic();
341 bool is_prefetch = inst->staticInst->isDataPrefetch();
342
343 /* If true, the trace's predicate value will be taken from the exec
344 * context predicate, otherwise, it will be set to false */
345 bool use_context_predicate = true;
346
347 if (response->fault != NoFault) {
348 /* Invoke memory faults. */
349 DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n",
350 response->fault->name());
351
352 if (inst->staticInst->isPrefetch()) {
353 DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n",
354 response->fault->name());
355
356 /* Don't assign to fault */
357 } else {
358 /* Take the fault raised during the TLB/memory access */
359 fault = response->fault;
360
361 fault->invoke(thread, inst->staticInst);
362 }
363 } else if (!packet) {
364 DPRINTF(MinorMem, "Completing failed request inst: %s\n",
365 *inst);
366 use_context_predicate = false;
367 if (!context.readMemAccPredicate())
368 inst->staticInst->completeAcc(nullptr, &context, inst->traceData);
369 } else if (packet->isError()) {
370 DPRINTF(MinorMem, "Trying to commit error response: %s\n",
371 *inst);
372
373 fatal("Received error response packet for inst: %s\n", *inst);
374 } else if (is_store || is_load || is_prefetch || is_atomic) {
375 assert(packet);
376
377 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n",
378 *inst, packet->getAddr(), packet->getSize());
379
380 if (is_load && packet->getSize() > 0) {
381 DPRINTF(MinorMem, "Memory data[0]: 0x%x\n",
382 static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0]));
383 }
384
385 /* Complete the memory access instruction */
386 fault = inst->staticInst->completeAcc(packet, &context,
387 inst->traceData);
388
389 if (fault != NoFault) {
390 /* Invoke fault created by instruction completion */
391 DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n",
392 fault->name());
393 fault->invoke(thread, inst->staticInst);
394 } else {
395 /* Stores need to be pushed into the store buffer to finish
396 * them off */
397 if (response->needsToBeSentToStoreBuffer())
398 lsq.sendStoreToStoreBuffer(response);
399 }
400 } else {
401 fatal("There should only ever be reads, "
402 "writes or faults at this point\n");
403 }
404
405 lsq.popResponse(response);
406
407 if (inst->traceData) {
408 inst->traceData->setPredicate((use_context_predicate ?
409 context.readPredicate() : false));
410 }
411
412 doInstCommitAccounting(inst);
413
414 /* Generate output to account for branches */
415 tryToBranch(inst, fault, branch);
416}
417
418bool
419Execute::isInterrupted(ThreadID thread_id) const
420{
421 return cpu.checkInterrupts(cpu.getContext(thread_id));
422}
423
424bool
425Execute::takeInterrupt(ThreadID thread_id, BranchData &branch)
426{
427 DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n",
428 cpu.getContext(thread_id)->pcState());
429
430 Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt
431 (cpu.getContext(thread_id));
432
433 if (interrupt != NoFault) {
434 /* The interrupt *must* set pcState */
435 cpu.getInterruptController(thread_id)->updateIntrInfo
436 (cpu.getContext(thread_id));
437 interrupt->invoke(cpu.getContext(thread_id));
438
439 assert(!lsq.accessesInFlight());
440
441 DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n",
442 interrupt->name(), cpu.getContext(thread_id)->pcState());
443
444 /* Assume that an interrupt *must* cause a branch. Assert this? */
445
446 updateBranchData(thread_id, BranchData::Interrupt,
447 MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(),
448 branch);
449 }
450
451 return interrupt != NoFault;
452}
453
454bool
455Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
456 bool &passed_predicate, Fault &fault)
457{
458 bool issued = false;
459
460 /* Set to true if the mem op. is issued and sent to the mem system */
461 passed_predicate = false;
462
463 if (!lsq.canRequest()) {
464 /* Not acting on instruction yet as the memory
465 * queues are full */
466 issued = false;
467 } else {
468 ThreadContext *thread = cpu.getContext(inst->id.threadId);
469 TheISA::PCState old_pc = thread->pcState();
470
471 ExecContext context(cpu, *cpu.threads[inst->id.threadId],
472 *this, inst);
473
474 DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst);
475
476 Fault init_fault = inst->staticInst->initiateAcc(&context,
477 inst->traceData);
478
479 if (init_fault != NoFault) {
480 DPRINTF(MinorExecute, "Fault on memory inst: %s"
481 " initiateAcc: %s\n", *inst, init_fault->name());
482 fault = init_fault;
483 } else {
484 /* Only set this if the instruction passed its
485 * predicate */
486 if (!context.readMemAccPredicate()) {
487 DPRINTF(MinorMem, "No memory access for inst: %s\n", *inst);
488 assert(context.readPredicate());
489 }
490 passed_predicate = context.readPredicate();
491
492 /* Set predicate in tracing */
493 if (inst->traceData)
494 inst->traceData->setPredicate(passed_predicate);
495
496 /* If the instruction didn't pass its predicate (and so will not
497 * progress from here) Try to branch to correct and branch
498 * mis-prediction. */
499 if (!passed_predicate) {
500 /* Leave it up to commit to handle the fault */
501 lsq.pushFailedRequest(inst);
502 }
503 }
504
505 /* Restore thread PC */
506 thread->pcState(old_pc);
507 issued = true;
508 }
509
510 return issued;
511}
512
513/** Increment a cyclic buffer index for indices [0, cycle_size-1] */
514inline unsigned int
515cyclicIndexInc(unsigned int index, unsigned int cycle_size)
516{
517 unsigned int ret = index + 1;
518
519 if (ret == cycle_size)
520 ret = 0;
521
522 return ret;
523}
524
525/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
526inline unsigned int
527cyclicIndexDec(unsigned int index, unsigned int cycle_size)
528{
529 int ret = index - 1;
530
531 if (ret < 0)
532 ret = cycle_size - 1;
533
534 return ret;
535}
536
537unsigned int
538Execute::issue(ThreadID thread_id)
539{
540 const ForwardInstData *insts_in = getInput(thread_id);
541 ExecuteThreadInfo &thread = executeInfo[thread_id];
542
543 /* Early termination if we have no instructions */
544 if (!insts_in)
545 return 0;
546
547 /* Start from the first FU */
548 unsigned int fu_index = 0;
549
550 /* Remains true while instructions are still being issued. If any
551 * instruction fails to issue, this is set to false and we exit issue.
552 * This strictly enforces in-order issue. For other issue behaviours,
553 * a more complicated test in the outer while loop below is needed. */
554 bool issued = true;
555
556 /* Number of insts issues this cycle to check for issueLimit */
557 unsigned num_insts_issued = 0;
558
559 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
560 unsigned num_mem_insts_issued = 0;
561
562 /* Number of instructions discarded this cycle in order to enforce a
563 * discardLimit. @todo, add that parameter? */
564 unsigned num_insts_discarded = 0;
565
566 do {
567 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex];
568 Fault fault = inst->fault;
569 bool discarded = false;
570 bool issued_mem_ref = false;
571
572 if (inst->isBubble()) {
573 /* Skip */
574 issued = true;
575 } else if (cpu.getContext(thread_id)->status() ==
576 ThreadContext::Suspended)
577 {
578 DPRINTF(MinorExecute, "Discarding inst: %s from suspended"
579 " thread\n", *inst);
580
581 issued = true;
582 discarded = true;
583 } else if (inst->id.streamSeqNum != thread.streamSeqNum) {
584 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
585 " state was unexpected, expected: %d\n",
586 *inst, thread.streamSeqNum);
587 issued = true;
588 discarded = true;
589 } else {
590 /* Try and issue an instruction into an FU, assume we didn't and
591 * fix that in the loop */
592 issued = false;
593
594 /* Try FU from 0 each instruction */
595 fu_index = 0;
596
597 /* Try and issue a single instruction stepping through the
598 * available FUs */
599 do {
600 FUPipeline *fu = funcUnits[fu_index];
601
602 DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n",
603 *inst, fu_index);
604
605 /* Does the examined fu have the OpClass-related capability
606 * needed to execute this instruction? Faults can always
607 * issue to any FU but probably should just 'live' in the
608 * inFlightInsts queue rather than having an FU. */
609 bool fu_is_capable = (!inst->isFault() ?
610 fu->provides(inst->staticInst->opClass()) : true);
611
612 if (inst->isNoCostInst()) {
613 /* Issue free insts. to a fake numbered FU */
614 fu_index = noCostFUIndex;
615
616 /* And start the countdown on activity to allow
617 * this instruction to get to the end of its FU */
618 cpu.activityRecorder->activity();
619
620 /* Mark the destinations for this instruction as
621 * busy */
622 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
623 Cycles(0), cpu.getContext(thread_id), false);
624
625 DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex);
626 inst->fuIndex = noCostFUIndex;
627 inst->extraCommitDelay = Cycles(0);
628 inst->extraCommitDelayExpr = NULL;
629
630 /* Push the instruction onto the inFlight queue so
631 * it can be committed in order */
632 QueuedInst fu_inst(inst);
633 thread.inFlightInsts->push(fu_inst);
634
635 issued = true;
636
637 } else if (!fu_is_capable || fu->alreadyPushed()) {
638 /* Skip */
639 if (!fu_is_capable) {
640 DPRINTF(MinorExecute, "Can't issue as FU: %d isn't"
641 " capable\n", fu_index);
642 } else {
643 DPRINTF(MinorExecute, "Can't issue as FU: %d is"
644 " already busy\n", fu_index);
645 }
646 } else if (fu->stalled) {
647 DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d,"
648 " it's stalled\n",
649 *inst, fu_index);
650 } else if (!fu->canInsert()) {
651 DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU"
652 " for another: %d cycles\n",
653 *inst, fu->cyclesBeforeInsert());
654 } else {
655 MinorFUTiming *timing = (!inst->isFault() ?
656 fu->findTiming(inst->staticInst) : NULL);
657
658 const std::vector<Cycles> *src_latencies =
659 (timing ? &(timing->srcRegsRelativeLats)
660 : NULL);
661
662 const std::vector<bool> *cant_forward_from_fu_indices =
663 &(fu->cantForwardFromFUIndices);
664
665 if (timing && timing->suppress) {
666 DPRINTF(MinorExecute, "Can't issue inst: %s as extra"
667 " decoding is suppressing it\n",
668 *inst);
669 } else if (!scoreboard[thread_id].canInstIssue(inst,
670 src_latencies, cant_forward_from_fu_indices,
671 cpu.curCycle(), cpu.getContext(thread_id)))
672 {
673 DPRINTF(MinorExecute, "Can't issue inst: %s yet\n",
674 *inst);
675 } else {
676 /* Can insert the instruction into this FU */
677 DPRINTF(MinorExecute, "Issuing inst: %s"
678 " into FU %d\n", *inst,
679 fu_index);
680
681 Cycles extra_dest_retire_lat = Cycles(0);
682 TimingExpr *extra_dest_retire_lat_expr = NULL;
683 Cycles extra_assumed_lat = Cycles(0);
684
685 /* Add the extraCommitDelay and extraAssumeLat to
686 * the FU pipeline timings */
687 if (timing) {
688 extra_dest_retire_lat =
689 timing->extraCommitLat;
690 extra_dest_retire_lat_expr =
691 timing->extraCommitLatExpr;
692 extra_assumed_lat =
693 timing->extraAssumedLat;
694 }
695
696 issued_mem_ref = inst->isMemRef();
697
698 QueuedInst fu_inst(inst);
699
700 /* Decorate the inst with FU details */
701 inst->fuIndex = fu_index;
702 inst->extraCommitDelay = extra_dest_retire_lat;
703 inst->extraCommitDelayExpr =
704 extra_dest_retire_lat_expr;
705
706 if (issued_mem_ref) {
707 /* Remember which instruction this memory op
708 * depends on so that initiateAcc can be called
709 * early */
710 if (allowEarlyMemIssue) {
711 inst->instToWaitFor =
712 scoreboard[thread_id].execSeqNumToWaitFor(inst,
713 cpu.getContext(thread_id));
714
715 if (lsq.getLastMemBarrier(thread_id) >
716 inst->instToWaitFor)
717 {
718 DPRINTF(MinorExecute, "A barrier will"
719 " cause a delay in mem ref issue of"
720 " inst: %s until after inst"
721 " %d(exec)\n", *inst,
722 lsq.getLastMemBarrier(thread_id));
723
724 inst->instToWaitFor =
725 lsq.getLastMemBarrier(thread_id);
726 } else {
727 DPRINTF(MinorExecute, "Memory ref inst:"
728 " %s must wait for inst %d(exec)"
729 " before issuing\n",
730 *inst, inst->instToWaitFor);
731 }
732
733 inst->canEarlyIssue = true;
734 }
735 /* Also queue this instruction in the memory ref
736 * queue to ensure in-order issue to the LSQ */
737 DPRINTF(MinorExecute, "Pushing mem inst: %s\n",
738 *inst);
739 thread.inFUMemInsts->push(fu_inst);
740 }
741
742 /* Issue to FU */
743 fu->push(fu_inst);
744 /* And start the countdown on activity to allow
745 * this instruction to get to the end of its FU */
746 cpu.activityRecorder->activity();
747
748 /* Mark the destinations for this instruction as
749 * busy */
750 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
751 fu->description.opLat +
752 extra_dest_retire_lat +
753 extra_assumed_lat,
754 cpu.getContext(thread_id),
755 issued_mem_ref && extra_assumed_lat == Cycles(0));
756
757 /* Push the instruction onto the inFlight queue so
758 * it can be committed in order */
759 thread.inFlightInsts->push(fu_inst);
760
761 issued = true;
762 }
763 }
764
765 fu_index++;
766 } while (fu_index != numFuncUnits && !issued);
767
768 if (!issued)
769 DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst);
770 }
771
772 if (issued) {
773 /* Generate MinorTrace's MinorInst lines. Do this at commit
774 * to allow better instruction annotation? */
775 if (DTRACE(MinorTrace) && !inst->isBubble())
776 inst->minorTraceInst(*this);
777
778 /* Mark up barriers in the LSQ */
779 if (!discarded && inst->isInst() &&
780 inst->staticInst->isMemBarrier())
781 {
782 DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst);
783 lsq.issuedMemBarrierInst(inst);
784 }
785
786 if (inst->traceData && setTraceTimeOnIssue) {
787 inst->traceData->setWhen(curTick());
788 }
789
790 if (issued_mem_ref)
791 num_mem_insts_issued++;
792
793 if (discarded) {
794 num_insts_discarded++;
795 } else if (!inst->isBubble()) {
796 num_insts_issued++;
797
798 if (num_insts_issued == issueLimit)
799 DPRINTF(MinorExecute, "Reached inst issue limit\n");
800 }
801
802 thread.inputIndex++;
803 DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n",
804 thread.inputIndex);
805 }
806
807 /* Got to the end of a line */
808 if (thread.inputIndex == insts_in->width()) {
809 popInput(thread_id);
810 /* Set insts_in to null to force us to leave the surrounding
811 * loop */
812 insts_in = NULL;
813
814 if (processMoreThanOneInput) {
815 DPRINTF(MinorExecute, "Wrapping\n");
816 insts_in = getInput(thread_id);
817 }
818 }
819 } while (insts_in && thread.inputIndex < insts_in->width() &&
820 /* We still have instructions */
821 fu_index != numFuncUnits && /* Not visited all FUs */
822 issued && /* We've not yet failed to issue an instruction */
823 num_insts_issued != issueLimit && /* Still allowed to issue */
824 num_mem_insts_issued != memoryIssueLimit);
825
826 return num_insts_issued;
827}
828
829bool
830Execute::tryPCEvents(ThreadID thread_id)
831{
832 ThreadContext *thread = cpu.getContext(thread_id);
833 unsigned int num_pc_event_checks = 0;
834
835 /* Handle PC events on instructions */
836 Addr oldPC;
837 do {
838 oldPC = thread->instAddr();
839 cpu.system->pcEventQueue.service(thread);
840 num_pc_event_checks++;
841 } while (oldPC != thread->instAddr());
842
843 if (num_pc_event_checks > 1) {
844 DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n",
845 thread->pcState());
846 }
847
848 return num_pc_event_checks > 1;
849}
850
851void
852Execute::doInstCommitAccounting(MinorDynInstPtr inst)
853{
854 assert(!inst->isFault());
855
856 MinorThread *thread = cpu.threads[inst->id.threadId];
857
858 /* Increment the many and various inst and op counts in the
859 * thread and system */
860 if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop())
861 {
862 thread->numInst++;
863 thread->numInsts++;
864 cpu.stats.numInsts++;
865 cpu.system->totalNumInsts++;
866
867 /* Act on events related to instruction counts */
868 cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst);
869 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts);
870 }
871 thread->numOp++;
872 thread->numOps++;
873 cpu.stats.numOps++;
874 cpu.stats.committedInstType[inst->id.threadId]
875 [inst->staticInst->opClass()]++;
876
877 /* Set the CP SeqNum to the numOps commit number */
878 if (inst->traceData)
879 inst->traceData->setCPSeq(thread->numOp);
880
881 cpu.probeInstCommit(inst->staticInst, inst->pc.instAddr());
882}
883
884bool
885Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue,
886 BranchData &branch, Fault &fault, bool &committed,
887 bool &completed_mem_issue)
888{
889 ThreadID thread_id = inst->id.threadId;
890 ThreadContext *thread = cpu.getContext(thread_id);
891
892 bool completed_inst = true;
893 fault = NoFault;
894
895 /* Is the thread for this instruction suspended? In that case, just
896 * stall as long as there are no pending interrupts */
897 if (thread->status() == ThreadContext::Suspended &&
898 !isInterrupted(thread_id))
899 {
900 panic("We should never hit the case where we try to commit from a "
901 "suspended thread as the streamSeqNum should not match");
902 } else if (inst->isFault()) {
903 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
904
905 DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n",
906 inst->fault->name());
907
908 fault = inst->fault;
909 inst->fault->invoke(thread, NULL);
910
911 tryToBranch(inst, fault, branch);
912 } else if (inst->staticInst->isMemRef()) {
913 /* Memory accesses are executed in two parts:
914 * executeMemRefInst -- calculates the EA and issues the access
915 * to memory. This is done here.
916 * handleMemResponse -- handles the response packet, done by
917 * Execute::commit
918 *
919 * While the memory access is in its FU, the EA is being
920 * calculated. At the end of the FU, when it is ready to
921 * 'commit' (in this function), the access is presented to the
922 * memory queues. When a response comes back from memory,
923 * Execute::commit will commit it.
924 */
925 bool predicate_passed = false;
926 bool completed_mem_inst = executeMemRefInst(inst, branch,
927 predicate_passed, fault);
928
929 if (completed_mem_inst && fault != NoFault) {
930 if (early_memory_issue) {
931 DPRINTF(MinorExecute, "Fault in early executing inst: %s\n",
932 fault->name());
933 /* Don't execute the fault, just stall the instruction
934 * until it gets to the head of inFlightInsts */
935 inst->canEarlyIssue = false;
936 /* Not completed as we'll come here again to pick up
937 * the fault when we get to the end of the FU */
938 completed_inst = false;
939 } else {
940 DPRINTF(MinorExecute, "Fault in execute: %s\n",
941 fault->name());
942 fault->invoke(thread, NULL);
943
944 tryToBranch(inst, fault, branch);
945 completed_inst = true;
946 }
947 } else {
948 completed_inst = completed_mem_inst;
949 }
950 completed_mem_issue = completed_inst;
951 } else if (inst->isInst() && inst->staticInst->isMemBarrier() &&
952 !lsq.canPushIntoStoreBuffer())
953 {
954 DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as"
955 " there isn't space in the store buffer\n", *inst);
956
957 completed_inst = false;
958 } else if (inst->isInst() && inst->staticInst->isQuiesce()
959 && !branch.isBubble()){
960 /* This instruction can suspend, need to be able to communicate
961 * backwards, so no other branches may evaluate this cycle*/
962 completed_inst = false;
963 } else {
964 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
965
966 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst);
967
968 fault = inst->staticInst->execute(&context,
969 inst->traceData);
970
971 /* Set the predicate for tracing and dump */
972 if (inst->traceData)
973 inst->traceData->setPredicate(context.readPredicate());
974
975 committed = true;
976
977 if (fault != NoFault) {
978 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n",
979 *inst, fault->name());
980 fault->invoke(thread, inst->staticInst);
981 }
982
983 doInstCommitAccounting(inst);
984 tryToBranch(inst, fault, branch);
985 }
986
987 if (completed_inst) {
988 /* Keep a copy of this instruction's predictionSeqNum just in case
989 * we need to issue a branch without an instruction (such as an
990 * interrupt) */
991 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum;
992
993 /* Check to see if this instruction suspended the current thread. */
994 if (!inst->isFault() &&
995 thread->status() == ThreadContext::Suspended &&
996 branch.isBubble() && /* It didn't branch too */
997 !isInterrupted(thread_id)) /* Don't suspend if we have
998 interrupts */
999 {
1000 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState();
1001
1002 assert(resume_pc.microPC() == 0);
1003
1004 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute"
1005 " inst: %s\n", thread_id, *inst);
1006
1007 cpu.stats.numFetchSuspends++;
1008
1009 updateBranchData(thread_id, BranchData::SuspendThread, inst,
1010 resume_pc, branch);
1011 }
1012 }
1013
1014 return completed_inst;
1015}
1016
1017void
1018Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard,
1019 BranchData &branch)
1020{
1021 Fault fault = NoFault;
1022 Cycles now = cpu.curCycle();
1023 ExecuteThreadInfo &ex_info = executeInfo[thread_id];
1024
1025 /**
1026 * Try and execute as many instructions from the end of FU pipelines as
1027 * possible. This *doesn't* include actually advancing the pipelines.
1028 *
1029 * We do this by looping on the front of the inFlightInsts queue for as
1030 * long as we can find the desired instruction at the end of the
1031 * functional unit it was issued to without seeing a branch or a fault.
1032 * In this function, these terms are used:
1033 * complete -- The instruction has finished its passage through
1034 * its functional unit and its fate has been decided
1035 * (committed, discarded, issued to the memory system)
1036 * commit -- The instruction is complete(d), not discarded and has
1037 * its effects applied to the CPU state
1038 * discard(ed) -- The instruction is complete but not committed
1039 * as its streamSeqNum disagrees with the current
1040 * Execute::streamSeqNum
1041 *
1042 * Commits are also possible from two other places:
1043 *
1044 * 1) Responses returning from the LSQ
1045 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1046 * than their position in the inFlightInsts queue, but after all
1047 * their dependencies are resolved.
1048 */
1049
1050 /* Has an instruction been completed? Once this becomes false, we stop
1051 * trying to complete instructions. */
1052 bool completed_inst = true;
1053
1054 /* Number of insts committed this cycle to check against commitLimit */
1055 unsigned int num_insts_committed = 0;
1056
1057 /* Number of memory access instructions committed to check against
1058 * memCommitLimit */
1059 unsigned int num_mem_refs_committed = 0;
1060
1061 if (only_commit_microops && !ex_info.inFlightInsts->empty()) {
1062 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n",
1063 *(ex_info.inFlightInsts->front().inst),
1064 ex_info.lastCommitWasEndOfMacroop);
1065 }
1066
1067 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */
1068 !branch.isStreamChange() && /* No real branch */
1069 fault == NoFault && /* No faults */
1070 completed_inst && /* Still finding instructions to execute */
| 252 /* Predicted to branch */
253 if (!must_branch) {
254 /* No branch was taken, change stream to get us back to the
255 * intended PC value */
256 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but"
257 " none happened inst: %s\n",
258 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
259
260 reason = BranchData::BadlyPredictedBranch;
261 } else if (inst->predictedTarget == target) {
262 /* Branch prediction got the right target, kill the branch and
263 * carry on.
264 * Note that this information to the branch predictor might get
265 * overwritten by a "real" branch during this cycle */
266 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly"
267 " inst: %s\n",
268 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
269
270 reason = BranchData::CorrectlyPredictedBranch;
271 } else {
272 /* Branch prediction got the wrong target */
273 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x"
274 " but got the wrong target (actual: 0x%x) inst: %s\n",
275 inst->pc.instAddr(), inst->predictedTarget.instAddr(),
276 target.instAddr(), *inst);
277
278 reason = BranchData::BadlyPredictedBranchTarget;
279 }
280 } else if (must_branch) {
281 /* Unpredicted branch */
282 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
283 inst->pc.instAddr(), target.instAddr(), *inst);
284
285 reason = BranchData::UnpredictedBranch;
286 } else {
287 /* No branch at all */
288 reason = BranchData::NoBranch;
289 }
290
291 updateBranchData(inst->id.threadId, reason, inst, target, branch);
292}
293
294void
295Execute::updateBranchData(
296 ThreadID tid,
297 BranchData::Reason reason,
298 MinorDynInstPtr inst, const TheISA::PCState &target,
299 BranchData &branch)
300{
301 if (reason != BranchData::NoBranch) {
302 /* Bump up the stream sequence number on a real branch*/
303 if (BranchData::isStreamChange(reason))
304 executeInfo[tid].streamSeqNum++;
305
306 /* Branches (even mis-predictions) don't change the predictionSeqNum,
307 * just the streamSeqNum */
308 branch = BranchData(reason, tid,
309 executeInfo[tid].streamSeqNum,
310 /* Maintaining predictionSeqNum if there's no inst is just a
311 * courtesy and looks better on minorview */
312 (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum
313 : inst->id.predictionSeqNum),
314 target, inst);
315
316 DPRINTF(Branch, "Branch data signalled: %s\n", branch);
317 }
318}
319
320void
321Execute::handleMemResponse(MinorDynInstPtr inst,
322 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
323{
324 ThreadID thread_id = inst->id.threadId;
325 ThreadContext *thread = cpu.getContext(thread_id);
326
327 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
328
329 PacketPtr packet = response->packet;
330
331 bool is_load = inst->staticInst->isLoad();
332 bool is_store = inst->staticInst->isStore();
333 bool is_atomic = inst->staticInst->isAtomic();
334 bool is_prefetch = inst->staticInst->isDataPrefetch();
335
336 /* If true, the trace's predicate value will be taken from the exec
337 * context predicate, otherwise, it will be set to false */
338 bool use_context_predicate = true;
339
340 if (response->fault != NoFault) {
341 /* Invoke memory faults. */
342 DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n",
343 response->fault->name());
344
345 if (inst->staticInst->isPrefetch()) {
346 DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n",
347 response->fault->name());
348
349 /* Don't assign to fault */
350 } else {
351 /* Take the fault raised during the TLB/memory access */
352 fault = response->fault;
353
354 fault->invoke(thread, inst->staticInst);
355 }
356 } else if (!packet) {
357 DPRINTF(MinorMem, "Completing failed request inst: %s\n",
358 *inst);
359 use_context_predicate = false;
360 if (!context.readMemAccPredicate())
361 inst->staticInst->completeAcc(nullptr, &context, inst->traceData);
362 } else if (packet->isError()) {
363 DPRINTF(MinorMem, "Trying to commit error response: %s\n",
364 *inst);
365
366 fatal("Received error response packet for inst: %s\n", *inst);
367 } else if (is_store || is_load || is_prefetch || is_atomic) {
368 assert(packet);
369
370 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n",
371 *inst, packet->getAddr(), packet->getSize());
372
373 if (is_load && packet->getSize() > 0) {
374 DPRINTF(MinorMem, "Memory data[0]: 0x%x\n",
375 static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0]));
376 }
377
378 /* Complete the memory access instruction */
379 fault = inst->staticInst->completeAcc(packet, &context,
380 inst->traceData);
381
382 if (fault != NoFault) {
383 /* Invoke fault created by instruction completion */
384 DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n",
385 fault->name());
386 fault->invoke(thread, inst->staticInst);
387 } else {
388 /* Stores need to be pushed into the store buffer to finish
389 * them off */
390 if (response->needsToBeSentToStoreBuffer())
391 lsq.sendStoreToStoreBuffer(response);
392 }
393 } else {
394 fatal("There should only ever be reads, "
395 "writes or faults at this point\n");
396 }
397
398 lsq.popResponse(response);
399
400 if (inst->traceData) {
401 inst->traceData->setPredicate((use_context_predicate ?
402 context.readPredicate() : false));
403 }
404
405 doInstCommitAccounting(inst);
406
407 /* Generate output to account for branches */
408 tryToBranch(inst, fault, branch);
409}
410
411bool
412Execute::isInterrupted(ThreadID thread_id) const
413{
414 return cpu.checkInterrupts(cpu.getContext(thread_id));
415}
416
417bool
418Execute::takeInterrupt(ThreadID thread_id, BranchData &branch)
419{
420 DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n",
421 cpu.getContext(thread_id)->pcState());
422
423 Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt
424 (cpu.getContext(thread_id));
425
426 if (interrupt != NoFault) {
427 /* The interrupt *must* set pcState */
428 cpu.getInterruptController(thread_id)->updateIntrInfo
429 (cpu.getContext(thread_id));
430 interrupt->invoke(cpu.getContext(thread_id));
431
432 assert(!lsq.accessesInFlight());
433
434 DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n",
435 interrupt->name(), cpu.getContext(thread_id)->pcState());
436
437 /* Assume that an interrupt *must* cause a branch. Assert this? */
438
439 updateBranchData(thread_id, BranchData::Interrupt,
440 MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(),
441 branch);
442 }
443
444 return interrupt != NoFault;
445}
446
447bool
448Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
449 bool &passed_predicate, Fault &fault)
450{
451 bool issued = false;
452
453 /* Set to true if the mem op. is issued and sent to the mem system */
454 passed_predicate = false;
455
456 if (!lsq.canRequest()) {
457 /* Not acting on instruction yet as the memory
458 * queues are full */
459 issued = false;
460 } else {
461 ThreadContext *thread = cpu.getContext(inst->id.threadId);
462 TheISA::PCState old_pc = thread->pcState();
463
464 ExecContext context(cpu, *cpu.threads[inst->id.threadId],
465 *this, inst);
466
467 DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst);
468
469 Fault init_fault = inst->staticInst->initiateAcc(&context,
470 inst->traceData);
471
472 if (init_fault != NoFault) {
473 DPRINTF(MinorExecute, "Fault on memory inst: %s"
474 " initiateAcc: %s\n", *inst, init_fault->name());
475 fault = init_fault;
476 } else {
477 /* Only set this if the instruction passed its
478 * predicate */
479 if (!context.readMemAccPredicate()) {
480 DPRINTF(MinorMem, "No memory access for inst: %s\n", *inst);
481 assert(context.readPredicate());
482 }
483 passed_predicate = context.readPredicate();
484
485 /* Set predicate in tracing */
486 if (inst->traceData)
487 inst->traceData->setPredicate(passed_predicate);
488
489 /* If the instruction didn't pass its predicate (and so will not
490 * progress from here) Try to branch to correct and branch
491 * mis-prediction. */
492 if (!passed_predicate) {
493 /* Leave it up to commit to handle the fault */
494 lsq.pushFailedRequest(inst);
495 }
496 }
497
498 /* Restore thread PC */
499 thread->pcState(old_pc);
500 issued = true;
501 }
502
503 return issued;
504}
505
506/** Increment a cyclic buffer index for indices [0, cycle_size-1] */
507inline unsigned int
508cyclicIndexInc(unsigned int index, unsigned int cycle_size)
509{
510 unsigned int ret = index + 1;
511
512 if (ret == cycle_size)
513 ret = 0;
514
515 return ret;
516}
517
518/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
519inline unsigned int
520cyclicIndexDec(unsigned int index, unsigned int cycle_size)
521{
522 int ret = index - 1;
523
524 if (ret < 0)
525 ret = cycle_size - 1;
526
527 return ret;
528}
529
530unsigned int
531Execute::issue(ThreadID thread_id)
532{
533 const ForwardInstData *insts_in = getInput(thread_id);
534 ExecuteThreadInfo &thread = executeInfo[thread_id];
535
536 /* Early termination if we have no instructions */
537 if (!insts_in)
538 return 0;
539
540 /* Start from the first FU */
541 unsigned int fu_index = 0;
542
543 /* Remains true while instructions are still being issued. If any
544 * instruction fails to issue, this is set to false and we exit issue.
545 * This strictly enforces in-order issue. For other issue behaviours,
546 * a more complicated test in the outer while loop below is needed. */
547 bool issued = true;
548
549 /* Number of insts issues this cycle to check for issueLimit */
550 unsigned num_insts_issued = 0;
551
552 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
553 unsigned num_mem_insts_issued = 0;
554
555 /* Number of instructions discarded this cycle in order to enforce a
556 * discardLimit. @todo, add that parameter? */
557 unsigned num_insts_discarded = 0;
558
559 do {
560 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex];
561 Fault fault = inst->fault;
562 bool discarded = false;
563 bool issued_mem_ref = false;
564
565 if (inst->isBubble()) {
566 /* Skip */
567 issued = true;
568 } else if (cpu.getContext(thread_id)->status() ==
569 ThreadContext::Suspended)
570 {
571 DPRINTF(MinorExecute, "Discarding inst: %s from suspended"
572 " thread\n", *inst);
573
574 issued = true;
575 discarded = true;
576 } else if (inst->id.streamSeqNum != thread.streamSeqNum) {
577 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
578 " state was unexpected, expected: %d\n",
579 *inst, thread.streamSeqNum);
580 issued = true;
581 discarded = true;
582 } else {
583 /* Try and issue an instruction into an FU, assume we didn't and
584 * fix that in the loop */
585 issued = false;
586
587 /* Try FU from 0 each instruction */
588 fu_index = 0;
589
590 /* Try and issue a single instruction stepping through the
591 * available FUs */
592 do {
593 FUPipeline *fu = funcUnits[fu_index];
594
595 DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n",
596 *inst, fu_index);
597
598 /* Does the examined fu have the OpClass-related capability
599 * needed to execute this instruction? Faults can always
600 * issue to any FU but probably should just 'live' in the
601 * inFlightInsts queue rather than having an FU. */
602 bool fu_is_capable = (!inst->isFault() ?
603 fu->provides(inst->staticInst->opClass()) : true);
604
605 if (inst->isNoCostInst()) {
606 /* Issue free insts. to a fake numbered FU */
607 fu_index = noCostFUIndex;
608
609 /* And start the countdown on activity to allow
610 * this instruction to get to the end of its FU */
611 cpu.activityRecorder->activity();
612
613 /* Mark the destinations for this instruction as
614 * busy */
615 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
616 Cycles(0), cpu.getContext(thread_id), false);
617
618 DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex);
619 inst->fuIndex = noCostFUIndex;
620 inst->extraCommitDelay = Cycles(0);
621 inst->extraCommitDelayExpr = NULL;
622
623 /* Push the instruction onto the inFlight queue so
624 * it can be committed in order */
625 QueuedInst fu_inst(inst);
626 thread.inFlightInsts->push(fu_inst);
627
628 issued = true;
629
630 } else if (!fu_is_capable || fu->alreadyPushed()) {
631 /* Skip */
632 if (!fu_is_capable) {
633 DPRINTF(MinorExecute, "Can't issue as FU: %d isn't"
634 " capable\n", fu_index);
635 } else {
636 DPRINTF(MinorExecute, "Can't issue as FU: %d is"
637 " already busy\n", fu_index);
638 }
639 } else if (fu->stalled) {
640 DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d,"
641 " it's stalled\n",
642 *inst, fu_index);
643 } else if (!fu->canInsert()) {
644 DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU"
645 " for another: %d cycles\n",
646 *inst, fu->cyclesBeforeInsert());
647 } else {
648 MinorFUTiming *timing = (!inst->isFault() ?
649 fu->findTiming(inst->staticInst) : NULL);
650
651 const std::vector<Cycles> *src_latencies =
652 (timing ? &(timing->srcRegsRelativeLats)
653 : NULL);
654
655 const std::vector<bool> *cant_forward_from_fu_indices =
656 &(fu->cantForwardFromFUIndices);
657
658 if (timing && timing->suppress) {
659 DPRINTF(MinorExecute, "Can't issue inst: %s as extra"
660 " decoding is suppressing it\n",
661 *inst);
662 } else if (!scoreboard[thread_id].canInstIssue(inst,
663 src_latencies, cant_forward_from_fu_indices,
664 cpu.curCycle(), cpu.getContext(thread_id)))
665 {
666 DPRINTF(MinorExecute, "Can't issue inst: %s yet\n",
667 *inst);
668 } else {
669 /* Can insert the instruction into this FU */
670 DPRINTF(MinorExecute, "Issuing inst: %s"
671 " into FU %d\n", *inst,
672 fu_index);
673
674 Cycles extra_dest_retire_lat = Cycles(0);
675 TimingExpr *extra_dest_retire_lat_expr = NULL;
676 Cycles extra_assumed_lat = Cycles(0);
677
678 /* Add the extraCommitDelay and extraAssumeLat to
679 * the FU pipeline timings */
680 if (timing) {
681 extra_dest_retire_lat =
682 timing->extraCommitLat;
683 extra_dest_retire_lat_expr =
684 timing->extraCommitLatExpr;
685 extra_assumed_lat =
686 timing->extraAssumedLat;
687 }
688
689 issued_mem_ref = inst->isMemRef();
690
691 QueuedInst fu_inst(inst);
692
693 /* Decorate the inst with FU details */
694 inst->fuIndex = fu_index;
695 inst->extraCommitDelay = extra_dest_retire_lat;
696 inst->extraCommitDelayExpr =
697 extra_dest_retire_lat_expr;
698
699 if (issued_mem_ref) {
700 /* Remember which instruction this memory op
701 * depends on so that initiateAcc can be called
702 * early */
703 if (allowEarlyMemIssue) {
704 inst->instToWaitFor =
705 scoreboard[thread_id].execSeqNumToWaitFor(inst,
706 cpu.getContext(thread_id));
707
708 if (lsq.getLastMemBarrier(thread_id) >
709 inst->instToWaitFor)
710 {
711 DPRINTF(MinorExecute, "A barrier will"
712 " cause a delay in mem ref issue of"
713 " inst: %s until after inst"
714 " %d(exec)\n", *inst,
715 lsq.getLastMemBarrier(thread_id));
716
717 inst->instToWaitFor =
718 lsq.getLastMemBarrier(thread_id);
719 } else {
720 DPRINTF(MinorExecute, "Memory ref inst:"
721 " %s must wait for inst %d(exec)"
722 " before issuing\n",
723 *inst, inst->instToWaitFor);
724 }
725
726 inst->canEarlyIssue = true;
727 }
728 /* Also queue this instruction in the memory ref
729 * queue to ensure in-order issue to the LSQ */
730 DPRINTF(MinorExecute, "Pushing mem inst: %s\n",
731 *inst);
732 thread.inFUMemInsts->push(fu_inst);
733 }
734
735 /* Issue to FU */
736 fu->push(fu_inst);
737 /* And start the countdown on activity to allow
738 * this instruction to get to the end of its FU */
739 cpu.activityRecorder->activity();
740
741 /* Mark the destinations for this instruction as
742 * busy */
743 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
744 fu->description.opLat +
745 extra_dest_retire_lat +
746 extra_assumed_lat,
747 cpu.getContext(thread_id),
748 issued_mem_ref && extra_assumed_lat == Cycles(0));
749
750 /* Push the instruction onto the inFlight queue so
751 * it can be committed in order */
752 thread.inFlightInsts->push(fu_inst);
753
754 issued = true;
755 }
756 }
757
758 fu_index++;
759 } while (fu_index != numFuncUnits && !issued);
760
761 if (!issued)
762 DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst);
763 }
764
765 if (issued) {
766 /* Generate MinorTrace's MinorInst lines. Do this at commit
767 * to allow better instruction annotation? */
768 if (DTRACE(MinorTrace) && !inst->isBubble())
769 inst->minorTraceInst(*this);
770
771 /* Mark up barriers in the LSQ */
772 if (!discarded && inst->isInst() &&
773 inst->staticInst->isMemBarrier())
774 {
775 DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst);
776 lsq.issuedMemBarrierInst(inst);
777 }
778
779 if (inst->traceData && setTraceTimeOnIssue) {
780 inst->traceData->setWhen(curTick());
781 }
782
783 if (issued_mem_ref)
784 num_mem_insts_issued++;
785
786 if (discarded) {
787 num_insts_discarded++;
788 } else if (!inst->isBubble()) {
789 num_insts_issued++;
790
791 if (num_insts_issued == issueLimit)
792 DPRINTF(MinorExecute, "Reached inst issue limit\n");
793 }
794
795 thread.inputIndex++;
796 DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n",
797 thread.inputIndex);
798 }
799
800 /* Got to the end of a line */
801 if (thread.inputIndex == insts_in->width()) {
802 popInput(thread_id);
803 /* Set insts_in to null to force us to leave the surrounding
804 * loop */
805 insts_in = NULL;
806
807 if (processMoreThanOneInput) {
808 DPRINTF(MinorExecute, "Wrapping\n");
809 insts_in = getInput(thread_id);
810 }
811 }
812 } while (insts_in && thread.inputIndex < insts_in->width() &&
813 /* We still have instructions */
814 fu_index != numFuncUnits && /* Not visited all FUs */
815 issued && /* We've not yet failed to issue an instruction */
816 num_insts_issued != issueLimit && /* Still allowed to issue */
817 num_mem_insts_issued != memoryIssueLimit);
818
819 return num_insts_issued;
820}
821
822bool
823Execute::tryPCEvents(ThreadID thread_id)
824{
825 ThreadContext *thread = cpu.getContext(thread_id);
826 unsigned int num_pc_event_checks = 0;
827
828 /* Handle PC events on instructions */
829 Addr oldPC;
830 do {
831 oldPC = thread->instAddr();
832 cpu.system->pcEventQueue.service(thread);
833 num_pc_event_checks++;
834 } while (oldPC != thread->instAddr());
835
836 if (num_pc_event_checks > 1) {
837 DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n",
838 thread->pcState());
839 }
840
841 return num_pc_event_checks > 1;
842}
843
844void
845Execute::doInstCommitAccounting(MinorDynInstPtr inst)
846{
847 assert(!inst->isFault());
848
849 MinorThread *thread = cpu.threads[inst->id.threadId];
850
851 /* Increment the many and various inst and op counts in the
852 * thread and system */
853 if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop())
854 {
855 thread->numInst++;
856 thread->numInsts++;
857 cpu.stats.numInsts++;
858 cpu.system->totalNumInsts++;
859
860 /* Act on events related to instruction counts */
861 cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst);
862 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts);
863 }
864 thread->numOp++;
865 thread->numOps++;
866 cpu.stats.numOps++;
867 cpu.stats.committedInstType[inst->id.threadId]
868 [inst->staticInst->opClass()]++;
869
870 /* Set the CP SeqNum to the numOps commit number */
871 if (inst->traceData)
872 inst->traceData->setCPSeq(thread->numOp);
873
874 cpu.probeInstCommit(inst->staticInst, inst->pc.instAddr());
875}
876
877bool
878Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue,
879 BranchData &branch, Fault &fault, bool &committed,
880 bool &completed_mem_issue)
881{
882 ThreadID thread_id = inst->id.threadId;
883 ThreadContext *thread = cpu.getContext(thread_id);
884
885 bool completed_inst = true;
886 fault = NoFault;
887
888 /* Is the thread for this instruction suspended? In that case, just
889 * stall as long as there are no pending interrupts */
890 if (thread->status() == ThreadContext::Suspended &&
891 !isInterrupted(thread_id))
892 {
893 panic("We should never hit the case where we try to commit from a "
894 "suspended thread as the streamSeqNum should not match");
895 } else if (inst->isFault()) {
896 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
897
898 DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n",
899 inst->fault->name());
900
901 fault = inst->fault;
902 inst->fault->invoke(thread, NULL);
903
904 tryToBranch(inst, fault, branch);
905 } else if (inst->staticInst->isMemRef()) {
906 /* Memory accesses are executed in two parts:
907 * executeMemRefInst -- calculates the EA and issues the access
908 * to memory. This is done here.
909 * handleMemResponse -- handles the response packet, done by
910 * Execute::commit
911 *
912 * While the memory access is in its FU, the EA is being
913 * calculated. At the end of the FU, when it is ready to
914 * 'commit' (in this function), the access is presented to the
915 * memory queues. When a response comes back from memory,
916 * Execute::commit will commit it.
917 */
918 bool predicate_passed = false;
919 bool completed_mem_inst = executeMemRefInst(inst, branch,
920 predicate_passed, fault);
921
922 if (completed_mem_inst && fault != NoFault) {
923 if (early_memory_issue) {
924 DPRINTF(MinorExecute, "Fault in early executing inst: %s\n",
925 fault->name());
926 /* Don't execute the fault, just stall the instruction
927 * until it gets to the head of inFlightInsts */
928 inst->canEarlyIssue = false;
929 /* Not completed as we'll come here again to pick up
930 * the fault when we get to the end of the FU */
931 completed_inst = false;
932 } else {
933 DPRINTF(MinorExecute, "Fault in execute: %s\n",
934 fault->name());
935 fault->invoke(thread, NULL);
936
937 tryToBranch(inst, fault, branch);
938 completed_inst = true;
939 }
940 } else {
941 completed_inst = completed_mem_inst;
942 }
943 completed_mem_issue = completed_inst;
944 } else if (inst->isInst() && inst->staticInst->isMemBarrier() &&
945 !lsq.canPushIntoStoreBuffer())
946 {
947 DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as"
948 " there isn't space in the store buffer\n", *inst);
949
950 completed_inst = false;
951 } else if (inst->isInst() && inst->staticInst->isQuiesce()
952 && !branch.isBubble()){
953 /* This instruction can suspend, need to be able to communicate
954 * backwards, so no other branches may evaluate this cycle*/
955 completed_inst = false;
956 } else {
957 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
958
959 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst);
960
961 fault = inst->staticInst->execute(&context,
962 inst->traceData);
963
964 /* Set the predicate for tracing and dump */
965 if (inst->traceData)
966 inst->traceData->setPredicate(context.readPredicate());
967
968 committed = true;
969
970 if (fault != NoFault) {
971 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n",
972 *inst, fault->name());
973 fault->invoke(thread, inst->staticInst);
974 }
975
976 doInstCommitAccounting(inst);
977 tryToBranch(inst, fault, branch);
978 }
979
980 if (completed_inst) {
981 /* Keep a copy of this instruction's predictionSeqNum just in case
982 * we need to issue a branch without an instruction (such as an
983 * interrupt) */
984 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum;
985
986 /* Check to see if this instruction suspended the current thread. */
987 if (!inst->isFault() &&
988 thread->status() == ThreadContext::Suspended &&
989 branch.isBubble() && /* It didn't branch too */
990 !isInterrupted(thread_id)) /* Don't suspend if we have
991 interrupts */
992 {
993 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState();
994
995 assert(resume_pc.microPC() == 0);
996
997 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute"
998 " inst: %s\n", thread_id, *inst);
999
1000 cpu.stats.numFetchSuspends++;
1001
1002 updateBranchData(thread_id, BranchData::SuspendThread, inst,
1003 resume_pc, branch);
1004 }
1005 }
1006
1007 return completed_inst;
1008}
1009
1010void
1011Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard,
1012 BranchData &branch)
1013{
1014 Fault fault = NoFault;
1015 Cycles now = cpu.curCycle();
1016 ExecuteThreadInfo &ex_info = executeInfo[thread_id];
1017
1018 /**
1019 * Try and execute as many instructions from the end of FU pipelines as
1020 * possible. This *doesn't* include actually advancing the pipelines.
1021 *
1022 * We do this by looping on the front of the inFlightInsts queue for as
1023 * long as we can find the desired instruction at the end of the
1024 * functional unit it was issued to without seeing a branch or a fault.
1025 * In this function, these terms are used:
1026 * complete -- The instruction has finished its passage through
1027 * its functional unit and its fate has been decided
1028 * (committed, discarded, issued to the memory system)
1029 * commit -- The instruction is complete(d), not discarded and has
1030 * its effects applied to the CPU state
1031 * discard(ed) -- The instruction is complete but not committed
1032 * as its streamSeqNum disagrees with the current
1033 * Execute::streamSeqNum
1034 *
1035 * Commits are also possible from two other places:
1036 *
1037 * 1) Responses returning from the LSQ
1038 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1039 * than their position in the inFlightInsts queue, but after all
1040 * their dependencies are resolved.
1041 */
1042
1043 /* Has an instruction been completed? Once this becomes false, we stop
1044 * trying to complete instructions. */
1045 bool completed_inst = true;
1046
1047 /* Number of insts committed this cycle to check against commitLimit */
1048 unsigned int num_insts_committed = 0;
1049
1050 /* Number of memory access instructions committed to check against
1051 * memCommitLimit */
1052 unsigned int num_mem_refs_committed = 0;
1053
1054 if (only_commit_microops && !ex_info.inFlightInsts->empty()) {
1055 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n",
1056 *(ex_info.inFlightInsts->front().inst),
1057 ex_info.lastCommitWasEndOfMacroop);
1058 }
1059
1060 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */
1061 !branch.isStreamChange() && /* No real branch */
1062 fault == NoFault && /* No faults */
1063 completed_inst && /* Still finding instructions to execute */
|
1071 num_insts_committed != commitLimit /* Not reached commit limit */
| 1064 num_insts_committed != commitLimit && /* Not reached commit limit */
1065 cpu.getContext(thread_id)->status() != ThreadContext::Suspended
|
1072 )
1073 {
1074 if (only_commit_microops) {
1075 DPRINTF(MinorInterrupt, "Committing tail of insts before"
1076 " interrupt: %s\n",
1077 *(ex_info.inFlightInsts->front().inst));
1078 }
1079
1080 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1081
1082 InstSeqNum head_exec_seq_num =
1083 head_inflight_inst->inst->id.execSeqNum;
1084
1085 /* The instruction we actually process if completed_inst
1086 * remains true to the end of the loop body.
1087 * Start by considering the the head of the in flight insts queue */
1088 MinorDynInstPtr inst = head_inflight_inst->inst;
1089
1090 bool committed_inst = false;
1091 bool discard_inst = false;
1092 bool completed_mem_ref = false;
1093 bool issued_mem_ref = false;
1094 bool early_memory_issue = false;
1095
1096 /* Must set this again to go around the loop */
1097 completed_inst = false;
1098
1099 /* If we're just completing a macroop before an interrupt or drain,
1100 * can we stil commit another microop (rather than a memory response)
1101 * without crosing into the next full instruction? */
1102 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1103 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop);
1104
1105 /* Can we find a mem response for this inst */
1106 LSQ::LSQRequestPtr mem_response =
1107 (inst->inLSQ ? lsq.findResponse(inst) : NULL);
1108
1109 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n",
1110 can_commit_insts);
1111
1112 /* Test for PC events after every instruction */
1113 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) {
1114 ThreadContext *thread = cpu.getContext(thread_id);
1115
1116 /* Branch as there was a change in PC */
1117 updateBranchData(thread_id, BranchData::UnpredictedBranch,
1118 MinorDynInst::bubble(), thread->pcState(), branch);
1119 } else if (mem_response &&
1120 num_mem_refs_committed < memoryCommitLimit)
1121 {
1122 /* Try to commit from the memory responses next */
1123 discard_inst = inst->id.streamSeqNum !=
1124 ex_info.streamSeqNum || discard;
1125
1126 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n",
1127 *inst);
1128
1129 /* Complete or discard the response */
1130 if (discard_inst) {
1131 DPRINTF(MinorExecute, "Discarding mem inst: %s as its"
1132 " stream state was unexpected, expected: %d\n",
1133 *inst, ex_info.streamSeqNum);
1134
1135 lsq.popResponse(mem_response);
1136 } else {
1137 handleMemResponse(inst, mem_response, branch, fault);
1138 committed_inst = true;
1139 }
1140
1141 completed_mem_ref = true;
1142 completed_inst = true;
1143 } else if (can_commit_insts) {
1144 /* If true, this instruction will, subject to timing tweaks,
1145 * be considered for completion. try_to_commit flattens
1146 * the `if' tree a bit and allows other tests for inst
1147 * commit to be inserted here. */
1148 bool try_to_commit = false;
1149
1150 /* Try and issue memory ops early if they:
1151 * - Can push a request into the LSQ
1152 * - Have reached the end of their FUs
1153 * - Have had all their dependencies satisfied
1154 * - Are from the right stream
1155 *
1156 * For any other case, leave it to the normal instruction
1157 * issue below to handle them.
1158 */
1159 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) {
1160 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n");
1161
1162 const MinorDynInstPtr head_mem_ref_inst =
1163 ex_info.inFUMemInsts->front().inst;
1164 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex];
1165 const MinorDynInstPtr &fu_inst = fu->front().inst;
1166
1167 /* Use this, possibly out of order, inst as the one
1168 * to 'commit'/send to the LSQ */
1169 if (!fu_inst->isBubble() &&
1170 !fu_inst->inLSQ &&
1171 fu_inst->canEarlyIssue &&
1172 ex_info.streamSeqNum == fu_inst->id.streamSeqNum &&
1173 head_exec_seq_num > fu_inst->instToWaitFor)
1174 {
1175 DPRINTF(MinorExecute, "Issuing mem ref early"
1176 " inst: %s instToWaitFor: %d\n",
1177 *(fu_inst), fu_inst->instToWaitFor);
1178
1179 inst = fu_inst;
1180 try_to_commit = true;
1181 early_memory_issue = true;
1182 completed_inst = true;
1183 }
1184 }
1185
1186 /* Try and commit FU-less insts */
1187 if (!completed_inst && inst->isNoCostInst()) {
1188 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst);
1189
1190 try_to_commit = true;
1191 completed_inst = true;
1192 }
1193
1194 /* Try to issue from the ends of FUs and the inFlightInsts
1195 * queue */
1196 if (!completed_inst && !inst->inLSQ) {
1197 DPRINTF(MinorExecute, "Trying to commit from FUs\n");
1198
1199 /* Try to commit from a functional unit */
1200 /* Is the head inst of the expected inst's FU actually the
1201 * expected inst? */
1202 QueuedInst &fu_inst =
1203 funcUnits[inst->fuIndex]->front();
1204 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum;
1205
1206 if (fu_inst.inst->isBubble()) {
1207 /* No instruction ready */
1208 completed_inst = false;
1209 } else if (fu_inst_seq_num != head_exec_seq_num) {
1210 /* Past instruction: we must have already executed it
1211 * in the same cycle and so the head inst isn't
1212 * actually at the end of its pipeline
1213 * Future instruction: handled above and only for
1214 * mem refs on their way to the LSQ */
1215 } else if (fu_inst.inst->id == inst->id) {
1216 /* All instructions can be committed if they have the
1217 * right execSeqNum and there are no in-flight
1218 * mem insts before us */
1219 try_to_commit = true;
1220 completed_inst = true;
1221 }
1222 }
1223
1224 if (try_to_commit) {
1225 discard_inst = inst->id.streamSeqNum !=
1226 ex_info.streamSeqNum || discard;
1227
1228 /* Is this instruction discardable as its streamSeqNum
1229 * doesn't match? */
1230 if (!discard_inst) {
1231 /* Try to commit or discard a non-memory instruction.
1232 * Memory ops are actually 'committed' from this FUs
1233 * and 'issued' into the memory system so we need to
1234 * account for them later (commit_was_mem_issue gets
1235 * set) */
1236 if (inst->extraCommitDelayExpr) {
1237 DPRINTF(MinorExecute, "Evaluating expression for"
1238 " extra commit delay inst: %s\n", *inst);
1239
1240 ThreadContext *thread = cpu.getContext(thread_id);
1241
1242 TimingExprEvalContext context(inst->staticInst,
1243 thread, NULL);
1244
1245 uint64_t extra_delay = inst->extraCommitDelayExpr->
1246 eval(context);
1247
1248 DPRINTF(MinorExecute, "Extra commit delay expr"
1249 " result: %d\n", extra_delay);
1250
1251 if (extra_delay < 128) {
1252 inst->extraCommitDelay += Cycles(extra_delay);
1253 } else {
1254 DPRINTF(MinorExecute, "Extra commit delay was"
1255 " very long: %d\n", extra_delay);
1256 }
1257 inst->extraCommitDelayExpr = NULL;
1258 }
1259
1260 /* Move the extraCommitDelay from the instruction
1261 * into the minimumCommitCycle */
1262 if (inst->extraCommitDelay != Cycles(0)) {
1263 inst->minimumCommitCycle = cpu.curCycle() +
1264 inst->extraCommitDelay;
1265 inst->extraCommitDelay = Cycles(0);
1266 }
1267
1268 /* @todo Think about making lastMemBarrier be
1269 * MAX_UINT_64 to avoid using 0 as a marker value */
1270 if (!inst->isFault() && inst->isMemRef() &&
1271 lsq.getLastMemBarrier(thread_id) <
1272 inst->id.execSeqNum &&
1273 lsq.getLastMemBarrier(thread_id) != 0)
1274 {
1275 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1276 " as there are incomplete barriers in flight\n",
1277 *inst);
1278 completed_inst = false;
1279 } else if (inst->minimumCommitCycle > now) {
1280 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1281 " as it wants to be stalled for %d more cycles\n",
1282 *inst, inst->minimumCommitCycle - now);
1283 completed_inst = false;
1284 } else {
1285 completed_inst = commitInst(inst,
1286 early_memory_issue, branch, fault,
1287 committed_inst, issued_mem_ref);
1288 }
1289 } else {
1290 /* Discard instruction */
1291 completed_inst = true;
1292 }
1293
1294 if (completed_inst) {
1295 /* Allow the pipeline to advance. If the FU head
1296 * instruction wasn't the inFlightInsts head
1297 * but had already been committed, it would have
1298 * unstalled the pipeline before here */
1299 if (inst->fuIndex != noCostFUIndex) {
1300 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id);
1301 funcUnits[inst->fuIndex]->stalled = false;
1302 }
1303 }
1304 }
1305 } else {
1306 DPRINTF(MinorExecute, "No instructions to commit\n");
1307 completed_inst = false;
1308 }
1309
1310 /* All discardable instructions must also be 'completed' by now */
1311 assert(!(discard_inst && !completed_inst));
1312
1313 /* Instruction committed but was discarded due to streamSeqNum
1314 * mismatch */
1315 if (discard_inst) {
1316 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
1317 " state was unexpected, expected: %d\n",
1318 *inst, ex_info.streamSeqNum);
1319
1320 if (fault == NoFault)
1321 cpu.stats.numDiscardedOps++;
1322 }
1323
1324 /* Mark the mem inst as being in the LSQ */
1325 if (issued_mem_ref) {
1326 inst->fuIndex = 0;
1327 inst->inLSQ = true;
1328 }
1329
1330 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1331 * as they've *definitely* exited the FUs */
1332 if (completed_inst && inst->isMemRef()) {
1333 /* The MemRef could have been discarded from the FU or the memory
1334 * queue, so just check an FU instruction */
1335 if (!ex_info.inFUMemInsts->empty() &&
1336 ex_info.inFUMemInsts->front().inst == inst)
1337 {
1338 ex_info.inFUMemInsts->pop();
1339 }
1340 }
1341
1342 if (completed_inst && !(issued_mem_ref && fault == NoFault)) {
1343 /* Note that this includes discarded insts */
1344 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst);
1345
1346 /* Got to the end of a full instruction? */
1347 ex_info.lastCommitWasEndOfMacroop = inst->isFault() ||
1348 inst->isLastOpInInst();
1349
1350 /* lastPredictionSeqNum is kept as a convenience to prevent its
1351 * value from changing too much on the minorview display */
1352 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum;
1353
1354 /* Finished with the inst, remove it from the inst queue and
1355 * clear its dependencies */
1356 ex_info.inFlightInsts->pop();
1357
1358 /* Complete barriers in the LSQ/move to store buffer */
1359 if (inst->isInst() && inst->staticInst->isMemBarrier()) {
1360 DPRINTF(MinorMem, "Completing memory barrier"
1361 " inst: %s committed: %d\n", *inst, committed_inst);
1362 lsq.completeMemBarrierInst(inst, committed_inst);
1363 }
1364
1365 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef());
1366 }
1367
1368 /* Handle per-cycle instruction counting */
1369 if (committed_inst) {
1370 bool is_no_cost_inst = inst->isNoCostInst();
1371
1372 /* Don't show no cost instructions as having taken a commit
1373 * slot */
1374 if (DTRACE(MinorTrace) && !is_no_cost_inst)
1375 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst;
1376
1377 if (!is_no_cost_inst)
1378 num_insts_committed++;
1379
1380 if (num_insts_committed == commitLimit)
1381 DPRINTF(MinorExecute, "Reached inst commit limit\n");
1382
1383 /* Re-set the time of the instruction if that's required for
1384 * tracing */
1385 if (inst->traceData) {
1386 if (setTraceTimeOnCommit)
1387 inst->traceData->setWhen(curTick());
1388 inst->traceData->dump();
1389 }
1390
1391 if (completed_mem_ref)
1392 num_mem_refs_committed++;
1393
1394 if (num_mem_refs_committed == memoryCommitLimit)
1395 DPRINTF(MinorExecute, "Reached mem ref commit limit\n");
1396 }
1397 }
1398}
1399
1400bool
1401Execute::isInbetweenInsts(ThreadID thread_id) const
1402{
1403 return executeInfo[thread_id].lastCommitWasEndOfMacroop &&
1404 !lsq.accessesInFlight();
1405}
1406
1407void
1408Execute::evaluate()
1409{
1410 if (!inp.outputWire->isBubble())
1411 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire);
1412
1413 BranchData &branch = *out.inputWire;
1414
1415 unsigned int num_issued = 0;
1416
1417 /* Do all the cycle-wise activities for dcachePort here to potentially
1418 * free up input spaces in the LSQ's requests queue */
1419 lsq.step();
1420
1421 /* Check interrupts first. Will halt commit if interrupt found */
1422 bool interrupted = false;
1423 ThreadID interrupt_tid = checkInterrupts(branch, interrupted);
1424
1425 if (interrupt_tid != InvalidThreadID) {
1426 /* Signalling an interrupt this cycle, not issuing/committing from
1427 * any other threads */
1428 } else if (!branch.isBubble()) {
1429 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1430 * without overwriting them */
1431 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old"
1432 " branch to complete\n");
1433 } else {
1434 ThreadID commit_tid = getCommittingThread();
1435
1436 if (commit_tid != InvalidThreadID) {
1437 ExecuteThreadInfo& commit_info = executeInfo[commit_tid];
1438
1439 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n",
1440 commit_tid);
1441 /* commit can set stalled flags observable to issue and so *must* be
1442 * called first */
1443 if (commit_info.drainState != NotDraining) {
1444 if (commit_info.drainState == DrainCurrentInst) {
1445 /* Commit only micro-ops, don't kill anything else */
1446 commit(commit_tid, true, false, branch);
1447
1448 if (isInbetweenInsts(commit_tid))
1449 setDrainState(commit_tid, DrainHaltFetch);
1450
1451 /* Discard any generated branch */
1452 branch = BranchData::bubble();
1453 } else if (commit_info.drainState == DrainAllInsts) {
1454 /* Kill all instructions */
1455 while (getInput(commit_tid))
1456 popInput(commit_tid);
1457 commit(commit_tid, false, true, branch);
1458 }
1459 } else {
1460 /* Commit micro-ops only if interrupted. Otherwise, commit
1461 * anything you like */
1462 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n",
1463 commit_tid);
1464 bool only_commit_microops = interrupted &&
1465 hasInterrupt(commit_tid);
1466 commit(commit_tid, only_commit_microops, false, branch);
1467 }
1468
1469 /* Halt fetch, but don't do it until we have the current instruction in
1470 * the bag */
1471 if (commit_info.drainState == DrainHaltFetch) {
1472 updateBranchData(commit_tid, BranchData::HaltFetch,
1473 MinorDynInst::bubble(), TheISA::PCState(0), branch);
1474
1475 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1476 setDrainState(commit_tid, DrainAllInsts);
1477 }
1478 }
1479 ThreadID issue_tid = getIssuingThread();
1480 /* This will issue merrily even when interrupted in the sure and
1481 * certain knowledge that the interrupt with change the stream */
1482 if (issue_tid != InvalidThreadID) {
1483 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n",
1484 issue_tid);
1485 num_issued = issue(issue_tid);
1486 }
1487
1488 }
1489
1490 /* Run logic to step functional units + decide if we are active on the next
1491 * clock cycle */
1492 std::vector<MinorDynInstPtr> next_issuable_insts;
1493 bool can_issue_next = false;
1494
1495 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1496 /* Find the next issuable instruction for each thread and see if it can
1497 be issued */
1498 if (getInput(tid)) {
1499 unsigned int input_index = executeInfo[tid].inputIndex;
1500 MinorDynInstPtr inst = getInput(tid)->insts[input_index];
1501 if (inst->isFault()) {
1502 can_issue_next = true;
1503 } else if (!inst->isBubble()) {
1504 next_issuable_insts.push_back(inst);
1505 }
1506 }
1507 }
1508
1509 bool becoming_stalled = true;
1510
1511 /* Advance the pipelines and note whether they still need to be
1512 * advanced */
1513 for (unsigned int i = 0; i < numFuncUnits; i++) {
1514 FUPipeline *fu = funcUnits[i];
1515 fu->advance();
1516
1517 /* If we need to tick again, the pipeline will have been left or set
1518 * to be unstalled */
1519 if (fu->occupancy !=0 && !fu->stalled)
1520 becoming_stalled = false;
1521
1522 /* Could we possibly issue the next instruction from any thread?
1523 * This is quite an expensive test and is only used to determine
1524 * if the CPU should remain active, only run it if we aren't sure
1525 * we are active next cycle yet */
1526 for (auto inst : next_issuable_insts) {
1527 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) &&
1528 scoreboard[inst->id.threadId].canInstIssue(inst,
1529 NULL, NULL, cpu.curCycle() + Cycles(1),
1530 cpu.getContext(inst->id.threadId))) {
1531 can_issue_next = true;
1532 break;
1533 }
1534 }
1535 }
1536
1537 bool head_inst_might_commit = false;
1538
1539 /* Could the head in flight insts be committed */
1540 for (auto const &info : executeInfo) {
1541 if (!info.inFlightInsts->empty()) {
1542 const QueuedInst &head_inst = info.inFlightInsts->front();
1543
1544 if (head_inst.inst->isNoCostInst()) {
1545 head_inst_might_commit = true;
1546 } else {
1547 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex];
1548 if ((fu->stalled &&
1549 fu->front().inst->id == head_inst.inst->id) ||
1550 lsq.findResponse(head_inst.inst))
1551 {
1552 head_inst_might_commit = true;
1553 break;
1554 }
1555 }
1556 }
1557 }
1558
1559 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1560 (num_issued != 0 ? " (issued some insts)" : ""),
1561 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"),
1562 (can_issue_next ? " (can issued next inst)" : ""),
1563 (head_inst_might_commit ? "(head inst might commit)" : ""),
1564 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""),
1565 (interrupted ? " (interrupted)" : ""));
1566
1567 bool need_to_tick =
1568 num_issued != 0 || /* Issued some insts this cycle */
1569 !becoming_stalled || /* Some FU pipelines can still move */
1570 can_issue_next || /* Can still issue a new inst */
1571 head_inst_might_commit || /* Could possible commit the next inst */
1572 lsq.needsToTick() || /* Must step the dcache port */
1573 interrupted; /* There are pending interrupts */
1574
1575 if (!need_to_tick) {
1576 DPRINTF(Activity, "The next cycle might be skippable as there are no"
1577 " advanceable FUs\n");
1578 }
1579
1580 /* Wake up if we need to tick again */
1581 if (need_to_tick)
1582 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1583
1584 /* Note activity of following buffer */
1585 if (!branch.isBubble())
1586 cpu.activityRecorder->activity();
1587
1588 /* Make sure the input (if any left) is pushed */
1589 if (!inp.outputWire->isBubble())
1590 inputBuffer[inp.outputWire->threadId].pushTail();
1591}
1592
1593ThreadID
1594Execute::checkInterrupts(BranchData& branch, bool& interrupted)
1595{
1596 ThreadID tid = interruptPriority;
1597 /* Evaluate interrupts in round-robin based upon service */
1598 do {
1599 /* Has an interrupt been signalled? This may not be acted on
1600 * straighaway so this is different from took_interrupt */
1601 bool thread_interrupted = false;
1602
1603 if (FullSystem && cpu.getInterruptController(tid)) {
1604 /* This is here because it seems that after drainResume the
1605 * interrupt controller isn't always set */
1606 thread_interrupted = executeInfo[tid].drainState == NotDraining &&
1607 isInterrupted(tid);
1608 interrupted = interrupted || thread_interrupted;
1609 } else {
1610 DPRINTF(MinorInterrupt, "No interrupt controller\n");
1611 }
1612 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1613 tid, thread_interrupted, isInbetweenInsts(tid));
1614 /* Act on interrupts */
1615 if (thread_interrupted && isInbetweenInsts(tid)) {
1616 if (takeInterrupt(tid, branch)) {
1617 interruptPriority = tid;
1618 return tid;
1619 }
1620 } else {
1621 tid = (tid + 1) % cpu.numThreads;
1622 }
1623 } while (tid != interruptPriority);
1624
1625 return InvalidThreadID;
1626}
1627
1628bool
1629Execute::hasInterrupt(ThreadID thread_id)
1630{
1631 if (FullSystem && cpu.getInterruptController(thread_id)) {
1632 return executeInfo[thread_id].drainState == NotDraining &&
1633 isInterrupted(thread_id);
1634 }
1635
1636 return false;
1637}
1638
1639void
1640Execute::minorTrace() const
1641{
1642 std::ostringstream insts;
1643 std::ostringstream stalled;
1644
1645 executeInfo[0].instsBeingCommitted.reportData(insts);
1646 lsq.minorTrace();
1647 inputBuffer[0].minorTrace();
1648 scoreboard[0].minorTrace();
1649
1650 /* Report functional unit stalling in one string */
1651 unsigned int i = 0;
1652 while (i < numFuncUnits)
1653 {
1654 stalled << (funcUnits[i]->stalled ? '1' : 'E');
1655 i++;
1656 if (i != numFuncUnits)
1657 stalled << ',';
1658 }
1659
1660 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1661 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1662 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum,
1663 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0));
1664
1665 std::for_each(funcUnits.begin(), funcUnits.end(),
1666 std::mem_fun(&FUPipeline::minorTrace));
1667
1668 executeInfo[0].inFlightInsts->minorTrace();
1669 executeInfo[0].inFUMemInsts->minorTrace();
1670}
1671
1672inline ThreadID
1673Execute::getCommittingThread()
1674{
1675 std::vector<ThreadID> priority_list;
1676
1677 switch (cpu.threadPolicy) {
1678 case Enums::SingleThreaded:
1679 return 0;
1680 case Enums::RoundRobin:
1681 priority_list = cpu.roundRobinPriority(commitPriority);
1682 break;
1683 case Enums::Random:
1684 priority_list = cpu.randomPriority();
1685 break;
1686 default:
1687 panic("Invalid thread policy");
1688 }
1689
1690 for (auto tid : priority_list) {
1691 ExecuteThreadInfo &ex_info = executeInfo[tid];
1692
1693 bool is_thread_active =
1694 cpu.getContext(tid)->status() == ThreadContext::Active;
1695 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1696 is_thread_active;
1697
1698 if (can_commit_insts) {
1699 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1700 MinorDynInstPtr inst = head_inflight_inst->inst;
1701
1702 can_commit_insts = can_commit_insts &&
1703 (!inst->inLSQ || (lsq.findResponse(inst) != NULL));
1704
1705 if (!inst->inLSQ) {
1706 bool can_transfer_mem_inst = false;
1707 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) {
1708 const MinorDynInstPtr head_mem_ref_inst =
1709 ex_info.inFUMemInsts->front().inst;
1710 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex];
1711 const MinorDynInstPtr &fu_inst = fu->front().inst;
1712 can_transfer_mem_inst =
1713 !fu_inst->isBubble() &&
1714 fu_inst->id.threadId == tid &&
1715 !fu_inst->inLSQ &&
1716 fu_inst->canEarlyIssue &&
1717 inst->id.execSeqNum > fu_inst->instToWaitFor;
1718 }
1719
1720 bool can_execute_fu_inst = inst->fuIndex == noCostFUIndex;
1721 if (can_commit_insts && !can_transfer_mem_inst &&
1722 inst->fuIndex != noCostFUIndex)
1723 {
1724 QueuedInst& fu_inst = funcUnits[inst->fuIndex]->front();
1725 can_execute_fu_inst = !fu_inst.inst->isBubble() &&
1726 fu_inst.inst->id == inst->id;
1727 }
1728
1729 can_commit_insts = can_commit_insts &&
1730 (can_transfer_mem_inst || can_execute_fu_inst);
1731 }
1732 }
1733
1734
1735 if (can_commit_insts) {
1736 commitPriority = tid;
1737 return tid;
1738 }
1739 }
1740
1741 return InvalidThreadID;
1742}
1743
1744inline ThreadID
1745Execute::getIssuingThread()
1746{
1747 std::vector<ThreadID> priority_list;
1748
1749 switch (cpu.threadPolicy) {
1750 case Enums::SingleThreaded:
1751 return 0;
1752 case Enums::RoundRobin:
1753 priority_list = cpu.roundRobinPriority(issuePriority);
1754 break;
1755 case Enums::Random:
1756 priority_list = cpu.randomPriority();
1757 break;
1758 default:
1759 panic("Invalid thread scheduling policy.");
1760 }
1761
1762 for (auto tid : priority_list) {
1763 if (cpu.getContext(tid)->status() == ThreadContext::Active &&
1764 getInput(tid)) {
1765 issuePriority = tid;
1766 return tid;
1767 }
1768 }
1769
1770 return InvalidThreadID;
1771}
1772
1773void
1774Execute::drainResume()
1775{
1776 DPRINTF(Drain, "MinorExecute drainResume\n");
1777
1778 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1779 setDrainState(tid, NotDraining);
1780 }
1781
1782 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1783}
1784
1785std::ostream &operator <<(std::ostream &os, Execute::DrainState state)
1786{
1787 switch (state)
1788 {
1789 case Execute::NotDraining:
1790 os << "NotDraining";
1791 break;
1792 case Execute::DrainCurrentInst:
1793 os << "DrainCurrentInst";
1794 break;
1795 case Execute::DrainHaltFetch:
1796 os << "DrainHaltFetch";
1797 break;
1798 case Execute::DrainAllInsts:
1799 os << "DrainAllInsts";
1800 break;
1801 default:
1802 os << "Drain-" << static_cast<int>(state);
1803 break;
1804 }
1805
1806 return os;
1807}
1808
1809void
1810Execute::setDrainState(ThreadID thread_id, DrainState state)
1811{
1812 DPRINTF(Drain, "setDrainState[%d]: %s\n", thread_id, state);
1813 executeInfo[thread_id].drainState = state;
1814}
1815
1816unsigned int
1817Execute::drain()
1818{
1819 DPRINTF(Drain, "MinorExecute drain\n");
1820
1821 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1822 if (executeInfo[tid].drainState == NotDraining) {
1823 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1824
1825 /* Go to DrainCurrentInst if we're between microops
1826 * or waiting on an unbufferable memory operation.
1827 * Otherwise we can go straight to DrainHaltFetch
1828 */
1829 if (isInbetweenInsts(tid))
1830 setDrainState(tid, DrainHaltFetch);
1831 else
1832 setDrainState(tid, DrainCurrentInst);
1833 }
1834 }
1835 return (isDrained() ? 0 : 1);
1836}
1837
1838bool
1839Execute::isDrained()
1840{
1841 if (!lsq.isDrained())
1842 return false;
1843
1844 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1845 if (!inputBuffer[tid].empty() ||
1846 !executeInfo[tid].inFlightInsts->empty()) {
1847
1848 return false;
1849 }
1850 }
1851
1852 return true;
1853}
1854
1855Execute::~Execute()
1856{
1857 for (unsigned int i = 0; i < numFuncUnits; i++)
1858 delete funcUnits[i];
1859
1860 for (ThreadID tid = 0; tid < cpu.numThreads; tid++)
1861 delete executeInfo[tid].inFlightInsts;
1862}
1863
1864bool
1865Execute::instIsRightStream(MinorDynInstPtr inst)
1866{
1867 return inst->id.streamSeqNum == executeInfo[inst->id.threadId].streamSeqNum;
1868}
1869
1870bool
1871Execute::instIsHeadInst(MinorDynInstPtr inst)
1872{
1873 bool ret = false;
1874
1875 if (!executeInfo[inst->id.threadId].inFlightInsts->empty())
1876 ret = executeInfo[inst->id.threadId].inFlightInsts->front().inst->id == inst->id;
1877
1878 return ret;
1879}
1880
1881MinorCPU::MinorCPUPort &
1882Execute::getDcachePort()
1883{
1884 return lsq.getDcachePort();
1885}
1886
1887}
| 1066 )
1067 {
1068 if (only_commit_microops) {
1069 DPRINTF(MinorInterrupt, "Committing tail of insts before"
1070 " interrupt: %s\n",
1071 *(ex_info.inFlightInsts->front().inst));
1072 }
1073
1074 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1075
1076 InstSeqNum head_exec_seq_num =
1077 head_inflight_inst->inst->id.execSeqNum;
1078
1079 /* The instruction we actually process if completed_inst
1080 * remains true to the end of the loop body.
1081 * Start by considering the the head of the in flight insts queue */
1082 MinorDynInstPtr inst = head_inflight_inst->inst;
1083
1084 bool committed_inst = false;
1085 bool discard_inst = false;
1086 bool completed_mem_ref = false;
1087 bool issued_mem_ref = false;
1088 bool early_memory_issue = false;
1089
1090 /* Must set this again to go around the loop */
1091 completed_inst = false;
1092
1093 /* If we're just completing a macroop before an interrupt or drain,
1094 * can we stil commit another microop (rather than a memory response)
1095 * without crosing into the next full instruction? */
1096 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1097 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop);
1098
1099 /* Can we find a mem response for this inst */
1100 LSQ::LSQRequestPtr mem_response =
1101 (inst->inLSQ ? lsq.findResponse(inst) : NULL);
1102
1103 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n",
1104 can_commit_insts);
1105
1106 /* Test for PC events after every instruction */
1107 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) {
1108 ThreadContext *thread = cpu.getContext(thread_id);
1109
1110 /* Branch as there was a change in PC */
1111 updateBranchData(thread_id, BranchData::UnpredictedBranch,
1112 MinorDynInst::bubble(), thread->pcState(), branch);
1113 } else if (mem_response &&
1114 num_mem_refs_committed < memoryCommitLimit)
1115 {
1116 /* Try to commit from the memory responses next */
1117 discard_inst = inst->id.streamSeqNum !=
1118 ex_info.streamSeqNum || discard;
1119
1120 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n",
1121 *inst);
1122
1123 /* Complete or discard the response */
1124 if (discard_inst) {
1125 DPRINTF(MinorExecute, "Discarding mem inst: %s as its"
1126 " stream state was unexpected, expected: %d\n",
1127 *inst, ex_info.streamSeqNum);
1128
1129 lsq.popResponse(mem_response);
1130 } else {
1131 handleMemResponse(inst, mem_response, branch, fault);
1132 committed_inst = true;
1133 }
1134
1135 completed_mem_ref = true;
1136 completed_inst = true;
1137 } else if (can_commit_insts) {
1138 /* If true, this instruction will, subject to timing tweaks,
1139 * be considered for completion. try_to_commit flattens
1140 * the `if' tree a bit and allows other tests for inst
1141 * commit to be inserted here. */
1142 bool try_to_commit = false;
1143
1144 /* Try and issue memory ops early if they:
1145 * - Can push a request into the LSQ
1146 * - Have reached the end of their FUs
1147 * - Have had all their dependencies satisfied
1148 * - Are from the right stream
1149 *
1150 * For any other case, leave it to the normal instruction
1151 * issue below to handle them.
1152 */
1153 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) {
1154 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n");
1155
1156 const MinorDynInstPtr head_mem_ref_inst =
1157 ex_info.inFUMemInsts->front().inst;
1158 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex];
1159 const MinorDynInstPtr &fu_inst = fu->front().inst;
1160
1161 /* Use this, possibly out of order, inst as the one
1162 * to 'commit'/send to the LSQ */
1163 if (!fu_inst->isBubble() &&
1164 !fu_inst->inLSQ &&
1165 fu_inst->canEarlyIssue &&
1166 ex_info.streamSeqNum == fu_inst->id.streamSeqNum &&
1167 head_exec_seq_num > fu_inst->instToWaitFor)
1168 {
1169 DPRINTF(MinorExecute, "Issuing mem ref early"
1170 " inst: %s instToWaitFor: %d\n",
1171 *(fu_inst), fu_inst->instToWaitFor);
1172
1173 inst = fu_inst;
1174 try_to_commit = true;
1175 early_memory_issue = true;
1176 completed_inst = true;
1177 }
1178 }
1179
1180 /* Try and commit FU-less insts */
1181 if (!completed_inst && inst->isNoCostInst()) {
1182 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst);
1183
1184 try_to_commit = true;
1185 completed_inst = true;
1186 }
1187
1188 /* Try to issue from the ends of FUs and the inFlightInsts
1189 * queue */
1190 if (!completed_inst && !inst->inLSQ) {
1191 DPRINTF(MinorExecute, "Trying to commit from FUs\n");
1192
1193 /* Try to commit from a functional unit */
1194 /* Is the head inst of the expected inst's FU actually the
1195 * expected inst? */
1196 QueuedInst &fu_inst =
1197 funcUnits[inst->fuIndex]->front();
1198 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum;
1199
1200 if (fu_inst.inst->isBubble()) {
1201 /* No instruction ready */
1202 completed_inst = false;
1203 } else if (fu_inst_seq_num != head_exec_seq_num) {
1204 /* Past instruction: we must have already executed it
1205 * in the same cycle and so the head inst isn't
1206 * actually at the end of its pipeline
1207 * Future instruction: handled above and only for
1208 * mem refs on their way to the LSQ */
1209 } else if (fu_inst.inst->id == inst->id) {
1210 /* All instructions can be committed if they have the
1211 * right execSeqNum and there are no in-flight
1212 * mem insts before us */
1213 try_to_commit = true;
1214 completed_inst = true;
1215 }
1216 }
1217
1218 if (try_to_commit) {
1219 discard_inst = inst->id.streamSeqNum !=
1220 ex_info.streamSeqNum || discard;
1221
1222 /* Is this instruction discardable as its streamSeqNum
1223 * doesn't match? */
1224 if (!discard_inst) {
1225 /* Try to commit or discard a non-memory instruction.
1226 * Memory ops are actually 'committed' from this FUs
1227 * and 'issued' into the memory system so we need to
1228 * account for them later (commit_was_mem_issue gets
1229 * set) */
1230 if (inst->extraCommitDelayExpr) {
1231 DPRINTF(MinorExecute, "Evaluating expression for"
1232 " extra commit delay inst: %s\n", *inst);
1233
1234 ThreadContext *thread = cpu.getContext(thread_id);
1235
1236 TimingExprEvalContext context(inst->staticInst,
1237 thread, NULL);
1238
1239 uint64_t extra_delay = inst->extraCommitDelayExpr->
1240 eval(context);
1241
1242 DPRINTF(MinorExecute, "Extra commit delay expr"
1243 " result: %d\n", extra_delay);
1244
1245 if (extra_delay < 128) {
1246 inst->extraCommitDelay += Cycles(extra_delay);
1247 } else {
1248 DPRINTF(MinorExecute, "Extra commit delay was"
1249 " very long: %d\n", extra_delay);
1250 }
1251 inst->extraCommitDelayExpr = NULL;
1252 }
1253
1254 /* Move the extraCommitDelay from the instruction
1255 * into the minimumCommitCycle */
1256 if (inst->extraCommitDelay != Cycles(0)) {
1257 inst->minimumCommitCycle = cpu.curCycle() +
1258 inst->extraCommitDelay;
1259 inst->extraCommitDelay = Cycles(0);
1260 }
1261
1262 /* @todo Think about making lastMemBarrier be
1263 * MAX_UINT_64 to avoid using 0 as a marker value */
1264 if (!inst->isFault() && inst->isMemRef() &&
1265 lsq.getLastMemBarrier(thread_id) <
1266 inst->id.execSeqNum &&
1267 lsq.getLastMemBarrier(thread_id) != 0)
1268 {
1269 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1270 " as there are incomplete barriers in flight\n",
1271 *inst);
1272 completed_inst = false;
1273 } else if (inst->minimumCommitCycle > now) {
1274 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1275 " as it wants to be stalled for %d more cycles\n",
1276 *inst, inst->minimumCommitCycle - now);
1277 completed_inst = false;
1278 } else {
1279 completed_inst = commitInst(inst,
1280 early_memory_issue, branch, fault,
1281 committed_inst, issued_mem_ref);
1282 }
1283 } else {
1284 /* Discard instruction */
1285 completed_inst = true;
1286 }
1287
1288 if (completed_inst) {
1289 /* Allow the pipeline to advance. If the FU head
1290 * instruction wasn't the inFlightInsts head
1291 * but had already been committed, it would have
1292 * unstalled the pipeline before here */
1293 if (inst->fuIndex != noCostFUIndex) {
1294 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id);
1295 funcUnits[inst->fuIndex]->stalled = false;
1296 }
1297 }
1298 }
1299 } else {
1300 DPRINTF(MinorExecute, "No instructions to commit\n");
1301 completed_inst = false;
1302 }
1303
1304 /* All discardable instructions must also be 'completed' by now */
1305 assert(!(discard_inst && !completed_inst));
1306
1307 /* Instruction committed but was discarded due to streamSeqNum
1308 * mismatch */
1309 if (discard_inst) {
1310 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
1311 " state was unexpected, expected: %d\n",
1312 *inst, ex_info.streamSeqNum);
1313
1314 if (fault == NoFault)
1315 cpu.stats.numDiscardedOps++;
1316 }
1317
1318 /* Mark the mem inst as being in the LSQ */
1319 if (issued_mem_ref) {
1320 inst->fuIndex = 0;
1321 inst->inLSQ = true;
1322 }
1323
1324 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1325 * as they've *definitely* exited the FUs */
1326 if (completed_inst && inst->isMemRef()) {
1327 /* The MemRef could have been discarded from the FU or the memory
1328 * queue, so just check an FU instruction */
1329 if (!ex_info.inFUMemInsts->empty() &&
1330 ex_info.inFUMemInsts->front().inst == inst)
1331 {
1332 ex_info.inFUMemInsts->pop();
1333 }
1334 }
1335
1336 if (completed_inst && !(issued_mem_ref && fault == NoFault)) {
1337 /* Note that this includes discarded insts */
1338 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst);
1339
1340 /* Got to the end of a full instruction? */
1341 ex_info.lastCommitWasEndOfMacroop = inst->isFault() ||
1342 inst->isLastOpInInst();
1343
1344 /* lastPredictionSeqNum is kept as a convenience to prevent its
1345 * value from changing too much on the minorview display */
1346 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum;
1347
1348 /* Finished with the inst, remove it from the inst queue and
1349 * clear its dependencies */
1350 ex_info.inFlightInsts->pop();
1351
1352 /* Complete barriers in the LSQ/move to store buffer */
1353 if (inst->isInst() && inst->staticInst->isMemBarrier()) {
1354 DPRINTF(MinorMem, "Completing memory barrier"
1355 " inst: %s committed: %d\n", *inst, committed_inst);
1356 lsq.completeMemBarrierInst(inst, committed_inst);
1357 }
1358
1359 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef());
1360 }
1361
1362 /* Handle per-cycle instruction counting */
1363 if (committed_inst) {
1364 bool is_no_cost_inst = inst->isNoCostInst();
1365
1366 /* Don't show no cost instructions as having taken a commit
1367 * slot */
1368 if (DTRACE(MinorTrace) && !is_no_cost_inst)
1369 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst;
1370
1371 if (!is_no_cost_inst)
1372 num_insts_committed++;
1373
1374 if (num_insts_committed == commitLimit)
1375 DPRINTF(MinorExecute, "Reached inst commit limit\n");
1376
1377 /* Re-set the time of the instruction if that's required for
1378 * tracing */
1379 if (inst->traceData) {
1380 if (setTraceTimeOnCommit)
1381 inst->traceData->setWhen(curTick());
1382 inst->traceData->dump();
1383 }
1384
1385 if (completed_mem_ref)
1386 num_mem_refs_committed++;
1387
1388 if (num_mem_refs_committed == memoryCommitLimit)
1389 DPRINTF(MinorExecute, "Reached mem ref commit limit\n");
1390 }
1391 }
1392}
1393
1394bool
1395Execute::isInbetweenInsts(ThreadID thread_id) const
1396{
1397 return executeInfo[thread_id].lastCommitWasEndOfMacroop &&
1398 !lsq.accessesInFlight();
1399}
1400
1401void
1402Execute::evaluate()
1403{
1404 if (!inp.outputWire->isBubble())
1405 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire);
1406
1407 BranchData &branch = *out.inputWire;
1408
1409 unsigned int num_issued = 0;
1410
1411 /* Do all the cycle-wise activities for dcachePort here to potentially
1412 * free up input spaces in the LSQ's requests queue */
1413 lsq.step();
1414
1415 /* Check interrupts first. Will halt commit if interrupt found */
1416 bool interrupted = false;
1417 ThreadID interrupt_tid = checkInterrupts(branch, interrupted);
1418
1419 if (interrupt_tid != InvalidThreadID) {
1420 /* Signalling an interrupt this cycle, not issuing/committing from
1421 * any other threads */
1422 } else if (!branch.isBubble()) {
1423 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1424 * without overwriting them */
1425 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old"
1426 " branch to complete\n");
1427 } else {
1428 ThreadID commit_tid = getCommittingThread();
1429
1430 if (commit_tid != InvalidThreadID) {
1431 ExecuteThreadInfo& commit_info = executeInfo[commit_tid];
1432
1433 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n",
1434 commit_tid);
1435 /* commit can set stalled flags observable to issue and so *must* be
1436 * called first */
1437 if (commit_info.drainState != NotDraining) {
1438 if (commit_info.drainState == DrainCurrentInst) {
1439 /* Commit only micro-ops, don't kill anything else */
1440 commit(commit_tid, true, false, branch);
1441
1442 if (isInbetweenInsts(commit_tid))
1443 setDrainState(commit_tid, DrainHaltFetch);
1444
1445 /* Discard any generated branch */
1446 branch = BranchData::bubble();
1447 } else if (commit_info.drainState == DrainAllInsts) {
1448 /* Kill all instructions */
1449 while (getInput(commit_tid))
1450 popInput(commit_tid);
1451 commit(commit_tid, false, true, branch);
1452 }
1453 } else {
1454 /* Commit micro-ops only if interrupted. Otherwise, commit
1455 * anything you like */
1456 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n",
1457 commit_tid);
1458 bool only_commit_microops = interrupted &&
1459 hasInterrupt(commit_tid);
1460 commit(commit_tid, only_commit_microops, false, branch);
1461 }
1462
1463 /* Halt fetch, but don't do it until we have the current instruction in
1464 * the bag */
1465 if (commit_info.drainState == DrainHaltFetch) {
1466 updateBranchData(commit_tid, BranchData::HaltFetch,
1467 MinorDynInst::bubble(), TheISA::PCState(0), branch);
1468
1469 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1470 setDrainState(commit_tid, DrainAllInsts);
1471 }
1472 }
1473 ThreadID issue_tid = getIssuingThread();
1474 /* This will issue merrily even when interrupted in the sure and
1475 * certain knowledge that the interrupt with change the stream */
1476 if (issue_tid != InvalidThreadID) {
1477 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n",
1478 issue_tid);
1479 num_issued = issue(issue_tid);
1480 }
1481
1482 }
1483
1484 /* Run logic to step functional units + decide if we are active on the next
1485 * clock cycle */
1486 std::vector<MinorDynInstPtr> next_issuable_insts;
1487 bool can_issue_next = false;
1488
1489 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1490 /* Find the next issuable instruction for each thread and see if it can
1491 be issued */
1492 if (getInput(tid)) {
1493 unsigned int input_index = executeInfo[tid].inputIndex;
1494 MinorDynInstPtr inst = getInput(tid)->insts[input_index];
1495 if (inst->isFault()) {
1496 can_issue_next = true;
1497 } else if (!inst->isBubble()) {
1498 next_issuable_insts.push_back(inst);
1499 }
1500 }
1501 }
1502
1503 bool becoming_stalled = true;
1504
1505 /* Advance the pipelines and note whether they still need to be
1506 * advanced */
1507 for (unsigned int i = 0; i < numFuncUnits; i++) {
1508 FUPipeline *fu = funcUnits[i];
1509 fu->advance();
1510
1511 /* If we need to tick again, the pipeline will have been left or set
1512 * to be unstalled */
1513 if (fu->occupancy !=0 && !fu->stalled)
1514 becoming_stalled = false;
1515
1516 /* Could we possibly issue the next instruction from any thread?
1517 * This is quite an expensive test and is only used to determine
1518 * if the CPU should remain active, only run it if we aren't sure
1519 * we are active next cycle yet */
1520 for (auto inst : next_issuable_insts) {
1521 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) &&
1522 scoreboard[inst->id.threadId].canInstIssue(inst,
1523 NULL, NULL, cpu.curCycle() + Cycles(1),
1524 cpu.getContext(inst->id.threadId))) {
1525 can_issue_next = true;
1526 break;
1527 }
1528 }
1529 }
1530
1531 bool head_inst_might_commit = false;
1532
1533 /* Could the head in flight insts be committed */
1534 for (auto const &info : executeInfo) {
1535 if (!info.inFlightInsts->empty()) {
1536 const QueuedInst &head_inst = info.inFlightInsts->front();
1537
1538 if (head_inst.inst->isNoCostInst()) {
1539 head_inst_might_commit = true;
1540 } else {
1541 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex];
1542 if ((fu->stalled &&
1543 fu->front().inst->id == head_inst.inst->id) ||
1544 lsq.findResponse(head_inst.inst))
1545 {
1546 head_inst_might_commit = true;
1547 break;
1548 }
1549 }
1550 }
1551 }
1552
1553 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1554 (num_issued != 0 ? " (issued some insts)" : ""),
1555 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"),
1556 (can_issue_next ? " (can issued next inst)" : ""),
1557 (head_inst_might_commit ? "(head inst might commit)" : ""),
1558 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""),
1559 (interrupted ? " (interrupted)" : ""));
1560
1561 bool need_to_tick =
1562 num_issued != 0 || /* Issued some insts this cycle */
1563 !becoming_stalled || /* Some FU pipelines can still move */
1564 can_issue_next || /* Can still issue a new inst */
1565 head_inst_might_commit || /* Could possible commit the next inst */
1566 lsq.needsToTick() || /* Must step the dcache port */
1567 interrupted; /* There are pending interrupts */
1568
1569 if (!need_to_tick) {
1570 DPRINTF(Activity, "The next cycle might be skippable as there are no"
1571 " advanceable FUs\n");
1572 }
1573
1574 /* Wake up if we need to tick again */
1575 if (need_to_tick)
1576 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1577
1578 /* Note activity of following buffer */
1579 if (!branch.isBubble())
1580 cpu.activityRecorder->activity();
1581
1582 /* Make sure the input (if any left) is pushed */
1583 if (!inp.outputWire->isBubble())
1584 inputBuffer[inp.outputWire->threadId].pushTail();
1585}
1586
1587ThreadID
1588Execute::checkInterrupts(BranchData& branch, bool& interrupted)
1589{
1590 ThreadID tid = interruptPriority;
1591 /* Evaluate interrupts in round-robin based upon service */
1592 do {
1593 /* Has an interrupt been signalled? This may not be acted on
1594 * straighaway so this is different from took_interrupt */
1595 bool thread_interrupted = false;
1596
1597 if (FullSystem && cpu.getInterruptController(tid)) {
1598 /* This is here because it seems that after drainResume the
1599 * interrupt controller isn't always set */
1600 thread_interrupted = executeInfo[tid].drainState == NotDraining &&
1601 isInterrupted(tid);
1602 interrupted = interrupted || thread_interrupted;
1603 } else {
1604 DPRINTF(MinorInterrupt, "No interrupt controller\n");
1605 }
1606 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1607 tid, thread_interrupted, isInbetweenInsts(tid));
1608 /* Act on interrupts */
1609 if (thread_interrupted && isInbetweenInsts(tid)) {
1610 if (takeInterrupt(tid, branch)) {
1611 interruptPriority = tid;
1612 return tid;
1613 }
1614 } else {
1615 tid = (tid + 1) % cpu.numThreads;
1616 }
1617 } while (tid != interruptPriority);
1618
1619 return InvalidThreadID;
1620}
1621
1622bool
1623Execute::hasInterrupt(ThreadID thread_id)
1624{
1625 if (FullSystem && cpu.getInterruptController(thread_id)) {
1626 return executeInfo[thread_id].drainState == NotDraining &&
1627 isInterrupted(thread_id);
1628 }
1629
1630 return false;
1631}
1632
1633void
1634Execute::minorTrace() const
1635{
1636 std::ostringstream insts;
1637 std::ostringstream stalled;
1638
1639 executeInfo[0].instsBeingCommitted.reportData(insts);
1640 lsq.minorTrace();
1641 inputBuffer[0].minorTrace();
1642 scoreboard[0].minorTrace();
1643
1644 /* Report functional unit stalling in one string */
1645 unsigned int i = 0;
1646 while (i < numFuncUnits)
1647 {
1648 stalled << (funcUnits[i]->stalled ? '1' : 'E');
1649 i++;
1650 if (i != numFuncUnits)
1651 stalled << ',';
1652 }
1653
1654 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1655 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1656 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum,
1657 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0));
1658
1659 std::for_each(funcUnits.begin(), funcUnits.end(),
1660 std::mem_fun(&FUPipeline::minorTrace));
1661
1662 executeInfo[0].inFlightInsts->minorTrace();
1663 executeInfo[0].inFUMemInsts->minorTrace();
1664}
1665
1666inline ThreadID
1667Execute::getCommittingThread()
1668{
1669 std::vector<ThreadID> priority_list;
1670
1671 switch (cpu.threadPolicy) {
1672 case Enums::SingleThreaded:
1673 return 0;
1674 case Enums::RoundRobin:
1675 priority_list = cpu.roundRobinPriority(commitPriority);
1676 break;
1677 case Enums::Random:
1678 priority_list = cpu.randomPriority();
1679 break;
1680 default:
1681 panic("Invalid thread policy");
1682 }
1683
1684 for (auto tid : priority_list) {
1685 ExecuteThreadInfo &ex_info = executeInfo[tid];
1686
1687 bool is_thread_active =
1688 cpu.getContext(tid)->status() == ThreadContext::Active;
1689 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1690 is_thread_active;
1691
1692 if (can_commit_insts) {
1693 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1694 MinorDynInstPtr inst = head_inflight_inst->inst;
1695
1696 can_commit_insts = can_commit_insts &&
1697 (!inst->inLSQ || (lsq.findResponse(inst) != NULL));
1698
1699 if (!inst->inLSQ) {
1700 bool can_transfer_mem_inst = false;
1701 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) {
1702 const MinorDynInstPtr head_mem_ref_inst =
1703 ex_info.inFUMemInsts->front().inst;
1704 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex];
1705 const MinorDynInstPtr &fu_inst = fu->front().inst;
1706 can_transfer_mem_inst =
1707 !fu_inst->isBubble() &&
1708 fu_inst->id.threadId == tid &&
1709 !fu_inst->inLSQ &&
1710 fu_inst->canEarlyIssue &&
1711 inst->id.execSeqNum > fu_inst->instToWaitFor;
1712 }
1713
1714 bool can_execute_fu_inst = inst->fuIndex == noCostFUIndex;
1715 if (can_commit_insts && !can_transfer_mem_inst &&
1716 inst->fuIndex != noCostFUIndex)
1717 {
1718 QueuedInst& fu_inst = funcUnits[inst->fuIndex]->front();
1719 can_execute_fu_inst = !fu_inst.inst->isBubble() &&
1720 fu_inst.inst->id == inst->id;
1721 }
1722
1723 can_commit_insts = can_commit_insts &&
1724 (can_transfer_mem_inst || can_execute_fu_inst);
1725 }
1726 }
1727
1728
1729 if (can_commit_insts) {
1730 commitPriority = tid;
1731 return tid;
1732 }
1733 }
1734
1735 return InvalidThreadID;
1736}
1737
1738inline ThreadID
1739Execute::getIssuingThread()
1740{
1741 std::vector<ThreadID> priority_list;
1742
1743 switch (cpu.threadPolicy) {
1744 case Enums::SingleThreaded:
1745 return 0;
1746 case Enums::RoundRobin:
1747 priority_list = cpu.roundRobinPriority(issuePriority);
1748 break;
1749 case Enums::Random:
1750 priority_list = cpu.randomPriority();
1751 break;
1752 default:
1753 panic("Invalid thread scheduling policy.");
1754 }
1755
1756 for (auto tid : priority_list) {
1757 if (cpu.getContext(tid)->status() == ThreadContext::Active &&
1758 getInput(tid)) {
1759 issuePriority = tid;
1760 return tid;
1761 }
1762 }
1763
1764 return InvalidThreadID;
1765}
1766
1767void
1768Execute::drainResume()
1769{
1770 DPRINTF(Drain, "MinorExecute drainResume\n");
1771
1772 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1773 setDrainState(tid, NotDraining);
1774 }
1775
1776 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1777}
1778
1779std::ostream &operator <<(std::ostream &os, Execute::DrainState state)
1780{
1781 switch (state)
1782 {
1783 case Execute::NotDraining:
1784 os << "NotDraining";
1785 break;
1786 case Execute::DrainCurrentInst:
1787 os << "DrainCurrentInst";
1788 break;
1789 case Execute::DrainHaltFetch:
1790 os << "DrainHaltFetch";
1791 break;
1792 case Execute::DrainAllInsts:
1793 os << "DrainAllInsts";
1794 break;
1795 default:
1796 os << "Drain-" << static_cast<int>(state);
1797 break;
1798 }
1799
1800 return os;
1801}
1802
1803void
1804Execute::setDrainState(ThreadID thread_id, DrainState state)
1805{
1806 DPRINTF(Drain, "setDrainState[%d]: %s\n", thread_id, state);
1807 executeInfo[thread_id].drainState = state;
1808}
1809
1810unsigned int
1811Execute::drain()
1812{
1813 DPRINTF(Drain, "MinorExecute drain\n");
1814
1815 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1816 if (executeInfo[tid].drainState == NotDraining) {
1817 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1818
1819 /* Go to DrainCurrentInst if we're between microops
1820 * or waiting on an unbufferable memory operation.
1821 * Otherwise we can go straight to DrainHaltFetch
1822 */
1823 if (isInbetweenInsts(tid))
1824 setDrainState(tid, DrainHaltFetch);
1825 else
1826 setDrainState(tid, DrainCurrentInst);
1827 }
1828 }
1829 return (isDrained() ? 0 : 1);
1830}
1831
1832bool
1833Execute::isDrained()
1834{
1835 if (!lsq.isDrained())
1836 return false;
1837
1838 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1839 if (!inputBuffer[tid].empty() ||
1840 !executeInfo[tid].inFlightInsts->empty()) {
1841
1842 return false;
1843 }
1844 }
1845
1846 return true;
1847}
1848
1849Execute::~Execute()
1850{
1851 for (unsigned int i = 0; i < numFuncUnits; i++)
1852 delete funcUnits[i];
1853
1854 for (ThreadID tid = 0; tid < cpu.numThreads; tid++)
1855 delete executeInfo[tid].inFlightInsts;
1856}
1857
1858bool
1859Execute::instIsRightStream(MinorDynInstPtr inst)
1860{
1861 return inst->id.streamSeqNum == executeInfo[inst->id.threadId].streamSeqNum;
1862}
1863
1864bool
1865Execute::instIsHeadInst(MinorDynInstPtr inst)
1866{
1867 bool ret = false;
1868
1869 if (!executeInfo[inst->id.threadId].inFlightInsts->empty())
1870 ret = executeInfo[inst->id.threadId].inFlightInsts->front().inst->id == inst->id;
1871
1872 return ret;
1873}
1874
1875MinorCPU::MinorCPUPort &
1876Execute::getDcachePort()
1877{
1878 return lsq.getDcachePort();
1879}
1880
1881}
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