1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/execute.hh"
41
42#include "arch/locked_mem.hh"
43#include "arch/registers.hh"
44#include "arch/utility.hh"
45#include "cpu/minor/cpu.hh"
46#include "cpu/minor/exec_context.hh"
47#include "cpu/minor/fetch1.hh"
48#include "cpu/minor/lsq.hh"
49#include "cpu/op_class.hh"
50#include "debug/Activity.hh"
51#include "debug/Branch.hh"
52#include "debug/Drain.hh"
53#include "debug/MinorExecute.hh"
54#include "debug/MinorInterrupt.hh"
55#include "debug/MinorMem.hh"
56#include "debug/MinorTrace.hh"
57#include "debug/PCEvent.hh"
58
59namespace Minor
60{
61
62Execute::Execute(const std::string &name_,
63 MinorCPU &cpu_,
64 MinorCPUParams ¶ms,
65 Latch<ForwardInstData>::Output inp_,
66 Latch<BranchData>::Input out_) :
67 Named(name_),
68 inp(inp_),
69 out(out_),
70 cpu(cpu_),
71 issueLimit(params.executeIssueLimit),
72 memoryIssueLimit(params.executeMemoryIssueLimit),
73 commitLimit(params.executeCommitLimit),
74 memoryCommitLimit(params.executeMemoryCommitLimit),
75 processMoreThanOneInput(params.executeCycleInput),
76 fuDescriptions(*params.executeFuncUnits),
77 numFuncUnits(fuDescriptions.funcUnits.size()),
78 setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit),
79 setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue),
80 allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue),
81 noCostFUIndex(fuDescriptions.funcUnits.size() + 1),
82 lsq(name_ + ".lsq", name_ + ".dcache_port",
83 cpu_, *this,
84 params.executeMaxAccessesInMemory,
85 params.executeMemoryWidth,
86 params.executeLSQRequestsQueueSize,
87 params.executeLSQTransfersQueueSize,
88 params.executeLSQStoreBufferSize,
89 params.executeLSQMaxStoreBufferStoresPerCycle),
90 executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)),
91 interruptPriority(0),
92 issuePriority(0),
93 commitPriority(0)
94{
95 if (commitLimit < 1) {
96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
97 commitLimit);
98 }
99
100 if (issueLimit < 1) {
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
102 issueLimit);
103 }
104
105 if (memoryIssueLimit < 1) {
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_,
107 memoryIssueLimit);
108 }
109
110 if (memoryCommitLimit > commitLimit) {
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
112 " executeCommitLimit (%d)\n",
113 name_, memoryCommitLimit, commitLimit);
114 }
115
116 if (params.executeInputBufferSize < 1) {
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
118 params.executeInputBufferSize);
119 }
120
121 if (params.executeInputBufferSize < 1) {
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
123 params.executeInputBufferSize);
124 }
125
126 /* This should be large enough to count all the in-FU instructions
127 * which need to be accounted for in the inFlightInsts
128 * queue */
129 unsigned int total_slots = 0;
130
131 /* Make FUPipelines for each MinorFU */
132 for (unsigned int i = 0; i < numFuncUnits; i++) {
133 std::ostringstream fu_name;
134 MinorFU *fu_description = fuDescriptions.funcUnits[i];
135
136 /* Note the total number of instruction slots (for sizing
137 * the inFlightInst queue) and the maximum latency of any FU
138 * (for sizing the activity recorder) */
139 total_slots += fu_description->opLat;
140
141 fu_name << name_ << ".fu." << i;
142
143 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu);
144
145 funcUnits.push_back(fu);
146 }
147
148 /** Check that there is a functional unit for all operation classes */
149 for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) {
150 bool found_fu = false;
151 unsigned int fu_index = 0;
152
153 while (fu_index < numFuncUnits && !found_fu)
154 {
155 if (funcUnits[fu_index]->provides(
156 static_cast<OpClass>(op_class)))
157 {
158 found_fu = true;
159 }
160 fu_index++;
161 }
162
163 if (!found_fu) {
164 warn("No functional unit for OpClass %s\n",
165 Enums::OpClassStrings[op_class]);
166 }
167 }
168
169 /* Per-thread structures */
170 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
171 std::string tid_str = std::to_string(tid);
172
173 /* Input Buffers */
174 inputBuffer.push_back(
175 InputBuffer<ForwardInstData>(
176 name_ + ".inputBuffer" + tid_str, "insts",
177 params.executeInputBufferSize));
178
179 /* Scoreboards */
180 scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
181
182 /* In-flight instruction records */
183 executeInfo[tid].inFlightInsts = new Queue<QueuedInst,
184 ReportTraitsAdaptor<QueuedInst> >(
185 name_ + ".inFlightInsts" + tid_str, "insts", total_slots);
186
187 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst,
188 ReportTraitsAdaptor<QueuedInst> >(
189 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots);
190 }
191}
192
193const ForwardInstData *
194Execute::getInput(ThreadID tid)
195{
196 /* Get a line from the inputBuffer to work with */
197 if (!inputBuffer[tid].empty()) {
198 const ForwardInstData &head = inputBuffer[tid].front();
199
200 return (head.isBubble() ? NULL : &(inputBuffer[tid].front()));
201 } else {
202 return NULL;
203 }
204}
205
206void
207Execute::popInput(ThreadID tid)
208{
209 if (!inputBuffer[tid].empty())
210 inputBuffer[tid].pop();
211
212 executeInfo[tid].inputIndex = 0;
213}
214
215void
216Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
217{
218 ThreadContext *thread = cpu.getContext(inst->id.threadId);
219 const TheISA::PCState &pc_before = inst->pc;
220 TheISA::PCState target = thread->pcState();
221
222 /* Force a branch for SerializeAfter/SquashAfter instructions
223 * at the end of micro-op sequence when we're not suspended */
224 bool force_branch = thread->status() != ThreadContext::Suspended &&
225 !inst->isFault() &&
226 inst->isLastOpInInst() &&
227 (inst->staticInst->isSerializeAfter() ||
228 inst->staticInst->isSquashAfter() ||
229 inst->staticInst->isIprAccess());
230
231 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
232 pc_before, target, (force_branch ? " (forcing)" : ""));
233
234 /* Will we change the PC to something other than the next instruction? */
235 bool must_branch = pc_before != target ||
236 fault != NoFault ||
237 force_branch;
238
239 /* The reason for the branch data we're about to generate, set below */
240 BranchData::Reason reason = BranchData::NoBranch;
241
242 if (fault == NoFault)
243 {
244 TheISA::advancePC(target, inst->staticInst);
245 thread->pcState(target);
246
247 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n",
248 pc_before, target);
249 }
250
251 if (inst->predictedTaken && !force_branch) {
252 /* Predicted to branch */
253 if (!must_branch) {
254 /* No branch was taken, change stream to get us back to the
255 * intended PC value */
256 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but"
257 " none happened inst: %s\n",
258 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
259
260 reason = BranchData::BadlyPredictedBranch;
261 } else if (inst->predictedTarget == target) {
262 /* Branch prediction got the right target, kill the branch and
263 * carry on.
264 * Note that this information to the branch predictor might get
265 * overwritten by a "real" branch during this cycle */
266 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly"
267 " inst: %s\n",
268 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
269
270 reason = BranchData::CorrectlyPredictedBranch;
271 } else {
272 /* Branch prediction got the wrong target */
273 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x"
274 " but got the wrong target (actual: 0x%x) inst: %s\n",
275 inst->pc.instAddr(), inst->predictedTarget.instAddr(),
276 target.instAddr(), *inst);
277
278 reason = BranchData::BadlyPredictedBranchTarget;
279 }
280 } else if (must_branch) {
281 /* Unpredicted branch */
282 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
283 inst->pc.instAddr(), target.instAddr(), *inst);
284
285 reason = BranchData::UnpredictedBranch;
286 } else {
287 /* No branch at all */
288 reason = BranchData::NoBranch;
289 }
290
291 updateBranchData(inst->id.threadId, reason, inst, target, branch);
292}
293
294void
295Execute::updateBranchData(
296 ThreadID tid,
297 BranchData::Reason reason,
298 MinorDynInstPtr inst, const TheISA::PCState &target,
299 BranchData &branch)
300{
301 if (reason != BranchData::NoBranch) {
302 /* Bump up the stream sequence number on a real branch*/
303 if (BranchData::isStreamChange(reason))
304 executeInfo[tid].streamSeqNum++;
305
306 /* Branches (even mis-predictions) don't change the predictionSeqNum,
307 * just the streamSeqNum */
308 branch = BranchData(reason, tid,
309 executeInfo[tid].streamSeqNum,
310 /* Maintaining predictionSeqNum if there's no inst is just a
311 * courtesy and looks better on minorview */
312 (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum
313 : inst->id.predictionSeqNum),
314 target, inst);
315
316 DPRINTF(Branch, "Branch data signalled: %s\n", branch);
317 }
318}
319
320void
321Execute::handleMemResponse(MinorDynInstPtr inst,
322 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
323{
324 ThreadID thread_id = inst->id.threadId;
325 ThreadContext *thread = cpu.getContext(thread_id);
326
327 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
328
329 PacketPtr packet = response->packet;
330
331 bool is_load = inst->staticInst->isLoad();
332 bool is_store = inst->staticInst->isStore();
333 bool is_prefetch = inst->staticInst->isDataPrefetch();
334
335 /* If true, the trace's predicate value will be taken from the exec
336 * context predicate, otherwise, it will be set to false */
337 bool use_context_predicate = true;
338
339 if (response->fault != NoFault) {
340 /* Invoke memory faults. */
341 DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n",
342 response->fault->name());
343
344 if (inst->staticInst->isPrefetch()) {
345 DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n",
346 response->fault->name());
347
348 /* Don't assign to fault */
349 } else {
350 /* Take the fault raised during the TLB/memory access */
351 fault = response->fault;
352
353 fault->invoke(thread, inst->staticInst);
354 }
355 } else if (!packet) {
356 DPRINTF(MinorMem, "Completing failed request inst: %s\n",
357 *inst);
358 use_context_predicate = false;
359 } else if (packet->isError()) {
360 DPRINTF(MinorMem, "Trying to commit error response: %s\n",
361 *inst);
362
363 fatal("Received error response packet for inst: %s\n", *inst);
364 } else if (is_store || is_load || is_prefetch) {
365 assert(packet);
366
367 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n",
368 *inst, packet->getAddr(), packet->getSize());
369
370 if (is_load && packet->getSize() > 0) {
371 DPRINTF(MinorMem, "Memory data[0]: 0x%x\n",
372 static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0]));
373 }
374
375 /* Complete the memory access instruction */
376 fault = inst->staticInst->completeAcc(packet, &context,
377 inst->traceData);
378
379 if (fault != NoFault) {
380 /* Invoke fault created by instruction completion */
381 DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n",
382 fault->name());
383 fault->invoke(thread, inst->staticInst);
384 } else {
385 /* Stores need to be pushed into the store buffer to finish
386 * them off */
387 if (response->needsToBeSentToStoreBuffer())
388 lsq.sendStoreToStoreBuffer(response);
389 }
390 } else {
391 fatal("There should only ever be reads, "
392 "writes or faults at this point\n");
393 }
394
395 lsq.popResponse(response);
396
397 if (inst->traceData) {
398 inst->traceData->setPredicate((use_context_predicate ?
399 context.readPredicate() : false));
400 }
401
402 doInstCommitAccounting(inst);
403
404 /* Generate output to account for branches */
405 tryToBranch(inst, fault, branch);
406}
407
408bool
409Execute::isInterrupted(ThreadID thread_id) const
410{
411 return cpu.checkInterrupts(cpu.getContext(thread_id));
412}
413
414bool
415Execute::takeInterrupt(ThreadID thread_id, BranchData &branch)
416{
417 DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n",
418 cpu.getContext(thread_id)->pcState());
419
420 Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt
421 (cpu.getContext(thread_id));
422
423 if (interrupt != NoFault) {
424 /* The interrupt *must* set pcState */
425 cpu.getInterruptController(thread_id)->updateIntrInfo
426 (cpu.getContext(thread_id));
427 interrupt->invoke(cpu.getContext(thread_id));
428
429 assert(!lsq.accessesInFlight());
430
431 DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n",
432 interrupt->name(), cpu.getContext(thread_id)->pcState());
433
434 /* Assume that an interrupt *must* cause a branch. Assert this? */
435
436 updateBranchData(thread_id, BranchData::Interrupt,
437 MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(),
438 branch);
439 }
440
441 return interrupt != NoFault;
442}
443
444bool
445Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
446 bool &passed_predicate, Fault &fault)
447{
448 bool issued = false;
449
450 /* Set to true if the mem op. is issued and sent to the mem system */
451 passed_predicate = false;
452
453 if (!lsq.canRequest()) {
454 /* Not acting on instruction yet as the memory
455 * queues are full */
456 issued = false;
457 } else {
458 ThreadContext *thread = cpu.getContext(inst->id.threadId);
459 TheISA::PCState old_pc = thread->pcState();
460
461 ExecContext context(cpu, *cpu.threads[inst->id.threadId],
462 *this, inst);
463
464 DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst);
465
466 Fault init_fault = inst->staticInst->initiateAcc(&context,
467 inst->traceData);
468
469 if (init_fault != NoFault) {
470 DPRINTF(MinorExecute, "Fault on memory inst: %s"
471 " initiateAcc: %s\n", *inst, init_fault->name());
472 fault = init_fault;
473 } else {
474 /* Only set this if the instruction passed its
475 * predicate */
476 passed_predicate = context.readPredicate();
477
478 /* Set predicate in tracing */
479 if (inst->traceData)
480 inst->traceData->setPredicate(passed_predicate);
481
482 /* If the instruction didn't pass its predicate (and so will not
483 * progress from here) Try to branch to correct and branch
484 * mis-prediction. */
485 if (!passed_predicate) {
486 /* Leave it up to commit to handle the fault */
487 lsq.pushFailedRequest(inst);
488 }
489 }
490
491 /* Restore thread PC */
492 thread->pcState(old_pc);
493 issued = true;
494 }
495
496 return issued;
497}
498
499/** Increment a cyclic buffer index for indices [0, cycle_size-1] */
500inline unsigned int
501cyclicIndexInc(unsigned int index, unsigned int cycle_size)
502{
503 unsigned int ret = index + 1;
504
505 if (ret == cycle_size)
506 ret = 0;
507
508 return ret;
509}
510
511/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
512inline unsigned int
513cyclicIndexDec(unsigned int index, unsigned int cycle_size)
514{
515 int ret = index - 1;
516
517 if (ret < 0)
518 ret = cycle_size - 1;
519
520 return ret;
521}
522
523unsigned int
524Execute::issue(ThreadID thread_id)
525{
526 const ForwardInstData *insts_in = getInput(thread_id);
527 ExecuteThreadInfo &thread = executeInfo[thread_id];
528
529 /* Early termination if we have no instructions */
530 if (!insts_in)
531 return 0;
532
533 /* Start from the first FU */
534 unsigned int fu_index = 0;
535
536 /* Remains true while instructions are still being issued. If any
537 * instruction fails to issue, this is set to false and we exit issue.
538 * This strictly enforces in-order issue. For other issue behaviours,
539 * a more complicated test in the outer while loop below is needed. */
540 bool issued = true;
541
542 /* Number of insts issues this cycle to check for issueLimit */
543 unsigned num_insts_issued = 0;
544
545 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
546 unsigned num_mem_insts_issued = 0;
547
548 /* Number of instructions discarded this cycle in order to enforce a
549 * discardLimit. @todo, add that parameter? */
550 unsigned num_insts_discarded = 0;
551
552 do {
553 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex];
554 Fault fault = inst->fault;
555 bool discarded = false;
556 bool issued_mem_ref = false;
557
558 if (inst->isBubble()) {
559 /* Skip */
560 issued = true;
561 } else if (cpu.getContext(thread_id)->status() ==
562 ThreadContext::Suspended)
563 {
564 DPRINTF(MinorExecute, "Discarding inst: %s from suspended"
565 " thread\n", *inst);
566
567 issued = true;
568 discarded = true;
569 } else if (inst->id.streamSeqNum != thread.streamSeqNum) {
570 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
571 " state was unexpected, expected: %d\n",
572 *inst, thread.streamSeqNum);
573 issued = true;
574 discarded = true;
575 } else {
576 /* Try and issue an instruction into an FU, assume we didn't and
577 * fix that in the loop */
578 issued = false;
579
580 /* Try FU from 0 each instruction */
581 fu_index = 0;
582
583 /* Try and issue a single instruction stepping through the
584 * available FUs */
585 do {
586 FUPipeline *fu = funcUnits[fu_index];
587
588 DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n",
589 *inst, fu_index);
590
591 /* Does the examined fu have the OpClass-related capability
592 * needed to execute this instruction? Faults can always
593 * issue to any FU but probably should just 'live' in the
594 * inFlightInsts queue rather than having an FU. */
595 bool fu_is_capable = (!inst->isFault() ?
596 fu->provides(inst->staticInst->opClass()) : true);
597
598 if (inst->isNoCostInst()) {
599 /* Issue free insts. to a fake numbered FU */
600 fu_index = noCostFUIndex;
601
602 /* And start the countdown on activity to allow
603 * this instruction to get to the end of its FU */
604 cpu.activityRecorder->activity();
605
606 /* Mark the destinations for this instruction as
607 * busy */
608 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
609 Cycles(0), cpu.getContext(thread_id), false);
610
611 DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex);
612 inst->fuIndex = noCostFUIndex;
613 inst->extraCommitDelay = Cycles(0);
614 inst->extraCommitDelayExpr = NULL;
615
616 /* Push the instruction onto the inFlight queue so
617 * it can be committed in order */
618 QueuedInst fu_inst(inst);
619 thread.inFlightInsts->push(fu_inst);
620
621 issued = true;
622
623 } else if (!fu_is_capable || fu->alreadyPushed()) {
624 /* Skip */
625 if (!fu_is_capable) {
626 DPRINTF(MinorExecute, "Can't issue as FU: %d isn't"
627 " capable\n", fu_index);
628 } else {
629 DPRINTF(MinorExecute, "Can't issue as FU: %d is"
630 " already busy\n", fu_index);
631 }
632 } else if (fu->stalled) {
633 DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d,"
634 " it's stalled\n",
635 *inst, fu_index);
636 } else if (!fu->canInsert()) {
637 DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU"
638 " for another: %d cycles\n",
639 *inst, fu->cyclesBeforeInsert());
640 } else {
641 MinorFUTiming *timing = (!inst->isFault() ?
642 fu->findTiming(inst->staticInst) : NULL);
643
644 const std::vector<Cycles> *src_latencies =
645 (timing ? &(timing->srcRegsRelativeLats)
646 : NULL);
647
648 const std::vector<bool> *cant_forward_from_fu_indices =
649 &(fu->cantForwardFromFUIndices);
650
651 if (timing && timing->suppress) {
652 DPRINTF(MinorExecute, "Can't issue inst: %s as extra"
653 " decoding is suppressing it\n",
654 *inst);
655 } else if (!scoreboard[thread_id].canInstIssue(inst,
656 src_latencies, cant_forward_from_fu_indices,
657 cpu.curCycle(), cpu.getContext(thread_id)))
658 {
659 DPRINTF(MinorExecute, "Can't issue inst: %s yet\n",
660 *inst);
661 } else {
662 /* Can insert the instruction into this FU */
663 DPRINTF(MinorExecute, "Issuing inst: %s"
664 " into FU %d\n", *inst,
665 fu_index);
666
667 Cycles extra_dest_retire_lat = Cycles(0);
668 TimingExpr *extra_dest_retire_lat_expr = NULL;
669 Cycles extra_assumed_lat = Cycles(0);
670
671 /* Add the extraCommitDelay and extraAssumeLat to
672 * the FU pipeline timings */
673 if (timing) {
674 extra_dest_retire_lat =
675 timing->extraCommitLat;
676 extra_dest_retire_lat_expr =
677 timing->extraCommitLatExpr;
678 extra_assumed_lat =
679 timing->extraAssumedLat;
680 }
681
682 issued_mem_ref = inst->isMemRef();
683
684 QueuedInst fu_inst(inst);
685
686 /* Decorate the inst with FU details */
687 inst->fuIndex = fu_index;
688 inst->extraCommitDelay = extra_dest_retire_lat;
689 inst->extraCommitDelayExpr =
690 extra_dest_retire_lat_expr;
691
692 if (issued_mem_ref) {
693 /* Remember which instruction this memory op
694 * depends on so that initiateAcc can be called
695 * early */
696 if (allowEarlyMemIssue) {
697 inst->instToWaitFor =
698 scoreboard[thread_id].execSeqNumToWaitFor(inst,
699 cpu.getContext(thread_id));
700
701 if (lsq.getLastMemBarrier(thread_id) >
702 inst->instToWaitFor)
703 {
704 DPRINTF(MinorExecute, "A barrier will"
705 " cause a delay in mem ref issue of"
706 " inst: %s until after inst"
707 " %d(exec)\n", *inst,
708 lsq.getLastMemBarrier(thread_id));
709
710 inst->instToWaitFor =
711 lsq.getLastMemBarrier(thread_id);
712 } else {
713 DPRINTF(MinorExecute, "Memory ref inst:"
714 " %s must wait for inst %d(exec)"
715 " before issuing\n",
716 *inst, inst->instToWaitFor);
717 }
718
719 inst->canEarlyIssue = true;
720 }
721 /* Also queue this instruction in the memory ref
722 * queue to ensure in-order issue to the LSQ */
723 DPRINTF(MinorExecute, "Pushing mem inst: %s\n",
724 *inst);
725 thread.inFUMemInsts->push(fu_inst);
726 }
727
728 /* Issue to FU */
729 fu->push(fu_inst);
730 /* And start the countdown on activity to allow
731 * this instruction to get to the end of its FU */
732 cpu.activityRecorder->activity();
733
734 /* Mark the destinations for this instruction as
735 * busy */
736 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
737 fu->description.opLat +
738 extra_dest_retire_lat +
739 extra_assumed_lat,
740 cpu.getContext(thread_id),
741 issued_mem_ref && extra_assumed_lat == Cycles(0));
742
743 /* Push the instruction onto the inFlight queue so
744 * it can be committed in order */
745 thread.inFlightInsts->push(fu_inst);
746
747 issued = true;
748 }
749 }
750
751 fu_index++;
752 } while (fu_index != numFuncUnits && !issued);
753
754 if (!issued)
755 DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst);
756 }
757
758 if (issued) {
759 /* Generate MinorTrace's MinorInst lines. Do this at commit
760 * to allow better instruction annotation? */
761 if (DTRACE(MinorTrace) && !inst->isBubble())
762 inst->minorTraceInst(*this);
763
764 /* Mark up barriers in the LSQ */
765 if (!discarded && inst->isInst() &&
766 inst->staticInst->isMemBarrier())
767 {
768 DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst);
769 lsq.issuedMemBarrierInst(inst);
770 }
771
772 if (inst->traceData && setTraceTimeOnIssue) {
773 inst->traceData->setWhen(curTick());
774 }
775
776 if (issued_mem_ref)
777 num_mem_insts_issued++;
778
779 if (discarded) {
780 num_insts_discarded++;
781 } else if (!inst->isBubble()) {
782 num_insts_issued++;
783
784 if (num_insts_issued == issueLimit)
785 DPRINTF(MinorExecute, "Reached inst issue limit\n");
786 }
787
788 thread.inputIndex++;
789 DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n",
790 thread.inputIndex);
791 }
792
793 /* Got to the end of a line */
794 if (thread.inputIndex == insts_in->width()) {
795 popInput(thread_id);
796 /* Set insts_in to null to force us to leave the surrounding
797 * loop */
798 insts_in = NULL;
799
800 if (processMoreThanOneInput) {
801 DPRINTF(MinorExecute, "Wrapping\n");
802 insts_in = getInput(thread_id);
803 }
804 }
805 } while (insts_in && thread.inputIndex < insts_in->width() &&
806 /* We still have instructions */
807 fu_index != numFuncUnits && /* Not visited all FUs */
808 issued && /* We've not yet failed to issue an instruction */
809 num_insts_issued != issueLimit && /* Still allowed to issue */
810 num_mem_insts_issued != memoryIssueLimit);
811
812 return num_insts_issued;
813}
814
815bool
816Execute::tryPCEvents(ThreadID thread_id)
817{
818 ThreadContext *thread = cpu.getContext(thread_id);
819 unsigned int num_pc_event_checks = 0;
820
821 /* Handle PC events on instructions */
822 Addr oldPC;
823 do {
824 oldPC = thread->instAddr();
825 cpu.system->pcEventQueue.service(thread);
826 num_pc_event_checks++;
827 } while (oldPC != thread->instAddr());
828
829 if (num_pc_event_checks > 1) {
830 DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n",
831 thread->pcState());
832 }
833
834 return num_pc_event_checks > 1;
835}
836
837void
838Execute::doInstCommitAccounting(MinorDynInstPtr inst)
839{
840 assert(!inst->isFault());
841
842 MinorThread *thread = cpu.threads[inst->id.threadId];
843
844 /* Increment the many and various inst and op counts in the
845 * thread and system */
846 if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop())
847 {
848 thread->numInst++;
849 thread->numInsts++;
850 cpu.stats.numInsts++;
851 cpu.system->totalNumInsts++;
852
853 /* Act on events related to instruction counts */
854 cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst);
855 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts);
856 }
857 thread->numOp++;
858 thread->numOps++;
859 cpu.stats.numOps++;
860 cpu.stats.committedInstType[inst->id.threadId]
861 [inst->staticInst->opClass()]++;
862
863 /* Set the CP SeqNum to the numOps commit number */
864 if (inst->traceData)
865 inst->traceData->setCPSeq(thread->numOp);
866
867 cpu.probeInstCommit(inst->staticInst);
868}
869
870bool
871Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue,
872 BranchData &branch, Fault &fault, bool &committed,
873 bool &completed_mem_issue)
874{
875 ThreadID thread_id = inst->id.threadId;
876 ThreadContext *thread = cpu.getContext(thread_id);
877
878 bool completed_inst = true;
879 fault = NoFault;
880
881 /* Is the thread for this instruction suspended? In that case, just
882 * stall as long as there are no pending interrupts */
883 if (thread->status() == ThreadContext::Suspended &&
884 !isInterrupted(thread_id))
885 {
886 panic("We should never hit the case where we try to commit from a "
887 "suspended thread as the streamSeqNum should not match");
888 } else if (inst->isFault()) {
889 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
890
891 DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n",
892 inst->fault->name());
893
894 fault = inst->fault;
895 inst->fault->invoke(thread, NULL);
896
897 tryToBranch(inst, fault, branch);
898 } else if (inst->staticInst->isMemRef()) {
899 /* Memory accesses are executed in two parts:
900 * executeMemRefInst -- calculates the EA and issues the access
901 * to memory. This is done here.
902 * handleMemResponse -- handles the response packet, done by
903 * Execute::commit
904 *
905 * While the memory access is in its FU, the EA is being
906 * calculated. At the end of the FU, when it is ready to
907 * 'commit' (in this function), the access is presented to the
908 * memory queues. When a response comes back from memory,
909 * Execute::commit will commit it.
910 */
911 bool predicate_passed = false;
912 bool completed_mem_inst = executeMemRefInst(inst, branch,
913 predicate_passed, fault);
914
915 if (completed_mem_inst && fault != NoFault) {
916 if (early_memory_issue) {
917 DPRINTF(MinorExecute, "Fault in early executing inst: %s\n",
918 fault->name());
919 /* Don't execute the fault, just stall the instruction
920 * until it gets to the head of inFlightInsts */
921 inst->canEarlyIssue = false;
922 /* Not completed as we'll come here again to pick up
923 * the fault when we get to the end of the FU */
924 completed_inst = false;
925 } else {
926 DPRINTF(MinorExecute, "Fault in execute: %s\n",
927 fault->name());
928 fault->invoke(thread, NULL);
929
930 tryToBranch(inst, fault, branch);
931 completed_inst = true;
932 }
933 } else {
934 completed_inst = completed_mem_inst;
935 }
936 completed_mem_issue = completed_inst;
937 } else if (inst->isInst() && inst->staticInst->isMemBarrier() &&
938 !lsq.canPushIntoStoreBuffer())
939 {
940 DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as"
941 " there isn't space in the store buffer\n", *inst);
942
943 completed_inst = false;
944 } else if (inst->isInst() && inst->staticInst->isQuiesce()
945 && !branch.isBubble()){
946 /* This instruction can suspend, need to be able to communicate
947 * backwards, so no other branches may evaluate this cycle*/
948 completed_inst = false;
949 } else {
950 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
951
952 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst);
953
954 fault = inst->staticInst->execute(&context,
955 inst->traceData);
956
957 /* Set the predicate for tracing and dump */
958 if (inst->traceData)
959 inst->traceData->setPredicate(context.readPredicate());
960
961 committed = true;
962
963 if (fault != NoFault) {
964 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n",
965 *inst, fault->name());
966 fault->invoke(thread, inst->staticInst);
967 }
968
969 doInstCommitAccounting(inst);
970 tryToBranch(inst, fault, branch);
971 }
972
973 if (completed_inst) {
974 /* Keep a copy of this instruction's predictionSeqNum just in case
975 * we need to issue a branch without an instruction (such as an
976 * interrupt) */
977 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum;
978
979 /* Check to see if this instruction suspended the current thread. */
980 if (!inst->isFault() &&
981 thread->status() == ThreadContext::Suspended &&
982 branch.isBubble() && /* It didn't branch too */
983 !isInterrupted(thread_id)) /* Don't suspend if we have
984 interrupts */
985 {
986 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState();
987
988 assert(resume_pc.microPC() == 0);
989
990 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute"
991 " inst: %s\n", thread_id, *inst);
992
993 cpu.stats.numFetchSuspends++;
994
995 updateBranchData(thread_id, BranchData::SuspendThread, inst,
996 resume_pc, branch);
997 }
998 }
999
1000 return completed_inst;
1001}
1002
1003void
1004Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard,
1005 BranchData &branch)
1006{
1007 Fault fault = NoFault;
1008 Cycles now = cpu.curCycle();
1009 ExecuteThreadInfo &ex_info = executeInfo[thread_id];
1010
1011 /**
1012 * Try and execute as many instructions from the end of FU pipelines as
1013 * possible. This *doesn't* include actually advancing the pipelines.
1014 *
1015 * We do this by looping on the front of the inFlightInsts queue for as
1016 * long as we can find the desired instruction at the end of the
1017 * functional unit it was issued to without seeing a branch or a fault.
1018 * In this function, these terms are used:
1019 * complete -- The instruction has finished its passage through
1020 * its functional unit and its fate has been decided
1021 * (committed, discarded, issued to the memory system)
1022 * commit -- The instruction is complete(d), not discarded and has
1023 * its effects applied to the CPU state
1024 * discard(ed) -- The instruction is complete but not committed
1025 * as its streamSeqNum disagrees with the current
1026 * Execute::streamSeqNum
1027 *
1028 * Commits are also possible from two other places:
1029 *
1030 * 1) Responses returning from the LSQ
1031 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1032 * than their position in the inFlightInsts queue, but after all
1033 * their dependencies are resolved.
1034 */
1035
1036 /* Has an instruction been completed? Once this becomes false, we stop
1037 * trying to complete instructions. */
1038 bool completed_inst = true;
1039
1040 /* Number of insts committed this cycle to check against commitLimit */
1041 unsigned int num_insts_committed = 0;
1042
1043 /* Number of memory access instructions committed to check against
1044 * memCommitLimit */
1045 unsigned int num_mem_refs_committed = 0;
1046
1047 if (only_commit_microops && !ex_info.inFlightInsts->empty()) {
1048 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n",
1049 *(ex_info.inFlightInsts->front().inst),
1050 ex_info.lastCommitWasEndOfMacroop);
1051 }
1052
1053 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */
1054 !branch.isStreamChange() && /* No real branch */
1055 fault == NoFault && /* No faults */
1056 completed_inst && /* Still finding instructions to execute */
1057 num_insts_committed != commitLimit && /* Not reached commit limit */
1058 cpu.getContext(thread_id)->status() != ThreadContext::Suspended
1059 )
1060 {
1061 if (only_commit_microops) {
1062 DPRINTF(MinorInterrupt, "Committing tail of insts before"
1063 " interrupt: %s\n",
1064 *(ex_info.inFlightInsts->front().inst));
1065 }
1066
1067 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1068
1069 InstSeqNum head_exec_seq_num =
1070 head_inflight_inst->inst->id.execSeqNum;
1071
1072 /* The instruction we actually process if completed_inst
1073 * remains true to the end of the loop body.
1074 * Start by considering the the head of the in flight insts queue */
1075 MinorDynInstPtr inst = head_inflight_inst->inst;
1076
1077 bool committed_inst = false;
1078 bool discard_inst = false;
1079 bool completed_mem_ref = false;
1080 bool issued_mem_ref = false;
1081 bool early_memory_issue = false;
1082
1083 /* Must set this again to go around the loop */
1084 completed_inst = false;
1085
1086 /* If we're just completing a macroop before an interrupt or drain,
1087 * can we stil commit another microop (rather than a memory response)
1088 * without crosing into the next full instruction? */
1089 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1090 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop);
1091
1092 /* Can we find a mem response for this inst */
1093 LSQ::LSQRequestPtr mem_response =
1094 (inst->inLSQ ? lsq.findResponse(inst) : NULL);
1095
1096 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n",
1097 can_commit_insts);
1098
1099 /* Test for PC events after every instruction */
1100 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) {
1101 ThreadContext *thread = cpu.getContext(thread_id);
1102
1103 /* Branch as there was a change in PC */
1104 updateBranchData(thread_id, BranchData::UnpredictedBranch,
1105 MinorDynInst::bubble(), thread->pcState(), branch);
1106 } else if (mem_response &&
1107 num_mem_refs_committed < memoryCommitLimit)
1108 {
1109 /* Try to commit from the memory responses next */
1110 discard_inst = inst->id.streamSeqNum !=
1111 ex_info.streamSeqNum || discard;
1112
1113 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n",
1114 *inst);
1115
1116 /* Complete or discard the response */
1117 if (discard_inst) {
1118 DPRINTF(MinorExecute, "Discarding mem inst: %s as its"
1119 " stream state was unexpected, expected: %d\n",
1120 *inst, ex_info.streamSeqNum);
1121
1122 lsq.popResponse(mem_response);
1123 } else {
1124 handleMemResponse(inst, mem_response, branch, fault);
1125 committed_inst = true;
1126 }
1127
1128 completed_mem_ref = true;
1129 completed_inst = true;
1130 } else if (can_commit_insts) {
1131 /* If true, this instruction will, subject to timing tweaks,
1132 * be considered for completion. try_to_commit flattens
1133 * the `if' tree a bit and allows other tests for inst
1134 * commit to be inserted here. */
1135 bool try_to_commit = false;
1136
1137 /* Try and issue memory ops early if they:
1138 * - Can push a request into the LSQ
1139 * - Have reached the end of their FUs
1140 * - Have had all their dependencies satisfied
1141 * - Are from the right stream
1142 *
1143 * For any other case, leave it to the normal instruction
1144 * issue below to handle them.
1145 */
1146 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) {
1147 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n");
1148
1149 const MinorDynInstPtr head_mem_ref_inst =
1150 ex_info.inFUMemInsts->front().inst;
1151 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex];
1152 const MinorDynInstPtr &fu_inst = fu->front().inst;
1153
1154 /* Use this, possibly out of order, inst as the one
1155 * to 'commit'/send to the LSQ */
1156 if (!fu_inst->isBubble() &&
1157 !fu_inst->inLSQ &&
1158 fu_inst->canEarlyIssue &&
1159 ex_info.streamSeqNum == fu_inst->id.streamSeqNum &&
1160 head_exec_seq_num > fu_inst->instToWaitFor)
1161 {
1162 DPRINTF(MinorExecute, "Issuing mem ref early"
1163 " inst: %s instToWaitFor: %d\n",
1164 *(fu_inst), fu_inst->instToWaitFor);
1165
1166 inst = fu_inst;
1167 try_to_commit = true;
1168 early_memory_issue = true;
1169 completed_inst = true;
1170 }
1171 }
1172
1173 /* Try and commit FU-less insts */
1174 if (!completed_inst && inst->isNoCostInst()) {
1175 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst);
1176
1177 try_to_commit = true;
1178 completed_inst = true;
1179 }
1180
1181 /* Try to issue from the ends of FUs and the inFlightInsts
1182 * queue */
1183 if (!completed_inst && !inst->inLSQ) {
1184 DPRINTF(MinorExecute, "Trying to commit from FUs\n");
1185
1186 /* Try to commit from a functional unit */
1187 /* Is the head inst of the expected inst's FU actually the
1188 * expected inst? */
1189 QueuedInst &fu_inst =
1190 funcUnits[inst->fuIndex]->front();
1191 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum;
1192
1193 if (fu_inst.inst->isBubble()) {
1194 /* No instruction ready */
1195 completed_inst = false;
1196 } else if (fu_inst_seq_num != head_exec_seq_num) {
1197 /* Past instruction: we must have already executed it
1198 * in the same cycle and so the head inst isn't
1199 * actually at the end of its pipeline
1200 * Future instruction: handled above and only for
1201 * mem refs on their way to the LSQ */
1202 } else if (fu_inst.inst->id == inst->id) {
1203 /* All instructions can be committed if they have the
1204 * right execSeqNum and there are no in-flight
1205 * mem insts before us */
1206 try_to_commit = true;
1207 completed_inst = true;
1208 }
1209 }
1210
1211 if (try_to_commit) {
1212 discard_inst = inst->id.streamSeqNum !=
1213 ex_info.streamSeqNum || discard;
1214
1215 /* Is this instruction discardable as its streamSeqNum
1216 * doesn't match? */
1217 if (!discard_inst) {
1218 /* Try to commit or discard a non-memory instruction.
1219 * Memory ops are actually 'committed' from this FUs
1220 * and 'issued' into the memory system so we need to
1221 * account for them later (commit_was_mem_issue gets
1222 * set) */
1223 if (inst->extraCommitDelayExpr) {
1224 DPRINTF(MinorExecute, "Evaluating expression for"
1225 " extra commit delay inst: %s\n", *inst);
1226
1227 ThreadContext *thread = cpu.getContext(thread_id);
1228
1229 TimingExprEvalContext context(inst->staticInst,
1230 thread, NULL);
1231
1232 uint64_t extra_delay = inst->extraCommitDelayExpr->
1233 eval(context);
1234
1235 DPRINTF(MinorExecute, "Extra commit delay expr"
1236 " result: %d\n", extra_delay);
1237
1238 if (extra_delay < 128) {
1239 inst->extraCommitDelay += Cycles(extra_delay);
1240 } else {
1241 DPRINTF(MinorExecute, "Extra commit delay was"
1242 " very long: %d\n", extra_delay);
1243 }
1244 inst->extraCommitDelayExpr = NULL;
1245 }
1246
1247 /* Move the extraCommitDelay from the instruction
1248 * into the minimumCommitCycle */
1249 if (inst->extraCommitDelay != Cycles(0)) {
1250 inst->minimumCommitCycle = cpu.curCycle() +
1251 inst->extraCommitDelay;
1252 inst->extraCommitDelay = Cycles(0);
1253 }
1254
1255 /* @todo Think about making lastMemBarrier be
1256 * MAX_UINT_64 to avoid using 0 as a marker value */
1257 if (!inst->isFault() && inst->isMemRef() &&
1258 lsq.getLastMemBarrier(thread_id) <
1259 inst->id.execSeqNum &&
1260 lsq.getLastMemBarrier(thread_id) != 0)
1261 {
1262 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1263 " as there are incomplete barriers in flight\n",
1264 *inst);
1265 completed_inst = false;
1266 } else if (inst->minimumCommitCycle > now) {
1267 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1268 " as it wants to be stalled for %d more cycles\n",
1269 *inst, inst->minimumCommitCycle - now);
1270 completed_inst = false;
1271 } else {
1272 completed_inst = commitInst(inst,
1273 early_memory_issue, branch, fault,
1274 committed_inst, issued_mem_ref);
1275 }
1276 } else {
1277 /* Discard instruction */
1278 completed_inst = true;
1279 }
1280
1281 if (completed_inst) {
1282 /* Allow the pipeline to advance. If the FU head
1283 * instruction wasn't the inFlightInsts head
1284 * but had already been committed, it would have
1285 * unstalled the pipeline before here */
1286 if (inst->fuIndex != noCostFUIndex) {
1287 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id);
1288 funcUnits[inst->fuIndex]->stalled = false;
1289 }
1290 }
1291 }
1292 } else {
1293 DPRINTF(MinorExecute, "No instructions to commit\n");
1294 completed_inst = false;
1295 }
1296
1297 /* All discardable instructions must also be 'completed' by now */
1298 assert(!(discard_inst && !completed_inst));
1299
1300 /* Instruction committed but was discarded due to streamSeqNum
1301 * mismatch */
1302 if (discard_inst) {
1303 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
1304 " state was unexpected, expected: %d\n",
1305 *inst, ex_info.streamSeqNum);
1306
1307 if (fault == NoFault)
1308 cpu.stats.numDiscardedOps++;
1309 }
1310
1311 /* Mark the mem inst as being in the LSQ */
1312 if (issued_mem_ref) {
1313 inst->fuIndex = 0;
1314 inst->inLSQ = true;
1315 }
1316
1317 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1318 * as they've *definitely* exited the FUs */
1319 if (completed_inst && inst->isMemRef()) {
1320 /* The MemRef could have been discarded from the FU or the memory
1321 * queue, so just check an FU instruction */
1322 if (!ex_info.inFUMemInsts->empty() &&
1323 ex_info.inFUMemInsts->front().inst == inst)
1324 {
1325 ex_info.inFUMemInsts->pop();
1326 }
1327 }
1328
1329 if (completed_inst && !(issued_mem_ref && fault == NoFault)) {
1330 /* Note that this includes discarded insts */
1331 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst);
1332
1333 /* Got to the end of a full instruction? */
1334 ex_info.lastCommitWasEndOfMacroop = inst->isFault() ||
1335 inst->isLastOpInInst();
1336
1337 /* lastPredictionSeqNum is kept as a convenience to prevent its
1338 * value from changing too much on the minorview display */
1339 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum;
1340
1341 /* Finished with the inst, remove it from the inst queue and
1342 * clear its dependencies */
1343 ex_info.inFlightInsts->pop();
1344
1345 /* Complete barriers in the LSQ/move to store buffer */
1346 if (inst->isInst() && inst->staticInst->isMemBarrier()) {
1347 DPRINTF(MinorMem, "Completing memory barrier"
1348 " inst: %s committed: %d\n", *inst, committed_inst);
1349 lsq.completeMemBarrierInst(inst, committed_inst);
1350 }
1351
1352 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef());
1353 }
1354
1355 /* Handle per-cycle instruction counting */
1356 if (committed_inst) {
1357 bool is_no_cost_inst = inst->isNoCostInst();
1358
1359 /* Don't show no cost instructions as having taken a commit
1360 * slot */
1361 if (DTRACE(MinorTrace) && !is_no_cost_inst)
1362 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst;
1363
1364 if (!is_no_cost_inst)
1365 num_insts_committed++;
1366
1367 if (num_insts_committed == commitLimit)
1368 DPRINTF(MinorExecute, "Reached inst commit limit\n");
1369
1370 /* Re-set the time of the instruction if that's required for
1371 * tracing */
1372 if (inst->traceData) {
1373 if (setTraceTimeOnCommit)
1374 inst->traceData->setWhen(curTick());
1375 inst->traceData->dump();
1376 }
1377
1378 if (completed_mem_ref)
1379 num_mem_refs_committed++;
1380
1381 if (num_mem_refs_committed == memoryCommitLimit)
1382 DPRINTF(MinorExecute, "Reached mem ref commit limit\n");
1383 }
1384 }
1385}
1386
1387bool
1388Execute::isInbetweenInsts(ThreadID thread_id) const
1389{
1390 return executeInfo[thread_id].lastCommitWasEndOfMacroop &&
1391 !lsq.accessesInFlight();
1392}
1393
1394void
1395Execute::evaluate()
1396{
1397 if (!inp.outputWire->isBubble())
1398 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire);
1399
1400 BranchData &branch = *out.inputWire;
1401
1402 unsigned int num_issued = 0;
1403
1404 /* Do all the cycle-wise activities for dcachePort here to potentially
1405 * free up input spaces in the LSQ's requests queue */
1406 lsq.step();
1407
1408 /* Check interrupts first. Will halt commit if interrupt found */
1409 bool interrupted = false;
1410 ThreadID interrupt_tid = checkInterrupts(branch, interrupted);
1411
1412 if (interrupt_tid != InvalidThreadID) {
1413 /* Signalling an interrupt this cycle, not issuing/committing from
1414 * any other threads */
1415 } else if (!branch.isBubble()) {
1416 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1417 * without overwriting them */
1418 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old"
1419 " branch to complete\n");
1420 } else {
1421 ThreadID commit_tid = getCommittingThread();
1422
1423 if (commit_tid != InvalidThreadID) {
1424 ExecuteThreadInfo& commit_info = executeInfo[commit_tid];
1425
1426 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n",
1427 commit_tid);
1428 /* commit can set stalled flags observable to issue and so *must* be
1429 * called first */
1430 if (commit_info.drainState != NotDraining) {
1431 if (commit_info.drainState == DrainCurrentInst) {
1432 /* Commit only micro-ops, don't kill anything else */
1433 commit(commit_tid, true, false, branch);
1434
1435 if (isInbetweenInsts(commit_tid))
1436 setDrainState(commit_tid, DrainHaltFetch);
1437
1438 /* Discard any generated branch */
1439 branch = BranchData::bubble();
1440 } else if (commit_info.drainState == DrainAllInsts) {
1441 /* Kill all instructions */
1442 while (getInput(commit_tid))
1443 popInput(commit_tid);
1444 commit(commit_tid, false, true, branch);
1445 }
1446 } else {
1447 /* Commit micro-ops only if interrupted. Otherwise, commit
1448 * anything you like */
1449 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n",
1450 commit_tid);
1451 bool only_commit_microops = interrupted &&
1452 hasInterrupt(commit_tid);
1453 commit(commit_tid, only_commit_microops, false, branch);
1454 }
1455
1456 /* Halt fetch, but don't do it until we have the current instruction in
1457 * the bag */
1458 if (commit_info.drainState == DrainHaltFetch) {
1459 updateBranchData(commit_tid, BranchData::HaltFetch,
1460 MinorDynInst::bubble(), TheISA::PCState(0), branch);
1461
1462 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1463 setDrainState(commit_tid, DrainAllInsts);
1464 }
1465 }
1466 ThreadID issue_tid = getIssuingThread();
1467 /* This will issue merrily even when interrupted in the sure and
1468 * certain knowledge that the interrupt with change the stream */
1469 if (issue_tid != InvalidThreadID) {
1470 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n",
1471 issue_tid);
1472 num_issued = issue(issue_tid);
1473 }
1474
1475 }
1476
1477 /* Run logic to step functional units + decide if we are active on the next
1478 * clock cycle */
1479 std::vector<MinorDynInstPtr> next_issuable_insts;
1480 bool can_issue_next = false;
1481
1482 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1483 /* Find the next issuable instruction for each thread and see if it can
1484 be issued */
1485 if (getInput(tid)) {
1486 unsigned int input_index = executeInfo[tid].inputIndex;
1487 MinorDynInstPtr inst = getInput(tid)->insts[input_index];
1488 if (inst->isFault()) {
1489 can_issue_next = true;
1490 } else if (!inst->isBubble()) {
1491 next_issuable_insts.push_back(inst);
1492 }
1493 }
1494 }
1495
1496 bool becoming_stalled = true;
1497
1498 /* Advance the pipelines and note whether they still need to be
1499 * advanced */
1500 for (unsigned int i = 0; i < numFuncUnits; i++) {
1501 FUPipeline *fu = funcUnits[i];
1502 fu->advance();
1503
1504 /* If we need to tick again, the pipeline will have been left or set
1505 * to be unstalled */
1506 if (fu->occupancy !=0 && !fu->stalled)
1507 becoming_stalled = false;
1508
1509 /* Could we possibly issue the next instruction from any thread?
1510 * This is quite an expensive test and is only used to determine
1511 * if the CPU should remain active, only run it if we aren't sure
1512 * we are active next cycle yet */
1513 for (auto inst : next_issuable_insts) {
1514 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) &&
1515 scoreboard[inst->id.threadId].canInstIssue(inst,
1516 NULL, NULL, cpu.curCycle() + Cycles(1),
1517 cpu.getContext(inst->id.threadId))) {
1518 can_issue_next = true;
1519 break;
1520 }
1521 }
1522 }
1523
1524 bool head_inst_might_commit = false;
1525
1526 /* Could the head in flight insts be committed */
1527 for (auto const &info : executeInfo) {
1528 if (!info.inFlightInsts->empty()) {
1529 const QueuedInst &head_inst = info.inFlightInsts->front();
1530
1531 if (head_inst.inst->isNoCostInst()) {
1532 head_inst_might_commit = true;
1533 } else {
1534 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex];
1535 if ((fu->stalled &&
1536 fu->front().inst->id == head_inst.inst->id) ||
1537 lsq.findResponse(head_inst.inst))
1538 {
1539 head_inst_might_commit = true;
1540 break;
1541 }
1542 }
1543 }
1544 }
1545
1546 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1547 (num_issued != 0 ? " (issued some insts)" : ""),
1548 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"),
1549 (can_issue_next ? " (can issued next inst)" : ""),
1550 (head_inst_might_commit ? "(head inst might commit)" : ""),
1551 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""),
1552 (interrupted ? " (interrupted)" : ""));
1553
1554 bool need_to_tick =
1555 num_issued != 0 || /* Issued some insts this cycle */
1556 !becoming_stalled || /* Some FU pipelines can still move */
1557 can_issue_next || /* Can still issue a new inst */
1558 head_inst_might_commit || /* Could possible commit the next inst */
1559 lsq.needsToTick() || /* Must step the dcache port */
1560 interrupted; /* There are pending interrupts */
1561
1562 if (!need_to_tick) {
1563 DPRINTF(Activity, "The next cycle might be skippable as there are no"
1564 " advanceable FUs\n");
1565 }
1566
1567 /* Wake up if we need to tick again */
1568 if (need_to_tick)
1569 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1570
1571 /* Note activity of following buffer */
1572 if (!branch.isBubble())
1573 cpu.activityRecorder->activity();
1574
1575 /* Make sure the input (if any left) is pushed */
1576 if (!inp.outputWire->isBubble())
1577 inputBuffer[inp.outputWire->threadId].pushTail();
1578}
1579
1580ThreadID
1581Execute::checkInterrupts(BranchData& branch, bool& interrupted)
1582{
1583 ThreadID tid = interruptPriority;
1584 /* Evaluate interrupts in round-robin based upon service */
1585 do {
1586 /* Has an interrupt been signalled? This may not be acted on
1587 * straighaway so this is different from took_interrupt */
1588 bool thread_interrupted = false;
1589
1590 if (FullSystem && cpu.getInterruptController(tid)) {
1591 /* This is here because it seems that after drainResume the
1592 * interrupt controller isn't always set */
1593 thread_interrupted = executeInfo[tid].drainState == NotDraining &&
1594 isInterrupted(tid);
1595 interrupted = interrupted || thread_interrupted;
1596 } else {
1597 DPRINTF(MinorInterrupt, "No interrupt controller\n");
1598 }
1599 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1600 tid, thread_interrupted, isInbetweenInsts(tid));
1601 /* Act on interrupts */
1602 if (thread_interrupted && isInbetweenInsts(tid)) {
1603 if (takeInterrupt(tid, branch)) {
1604 interruptPriority = tid;
1605 return tid;
1606 }
1607 } else {
1608 tid = (tid + 1) % cpu.numThreads;
1609 }
1610 } while (tid != interruptPriority);
1611
1612 return InvalidThreadID;
1613}
1614
1615bool
1616Execute::hasInterrupt(ThreadID thread_id)
1617{
1618 if (FullSystem && cpu.getInterruptController(thread_id)) {
1619 return executeInfo[thread_id].drainState == NotDraining &&
1620 isInterrupted(thread_id);
1621 }
1622
1623 return false;
1624}
1625
1626void
1627Execute::minorTrace() const
1628{
1629 std::ostringstream insts;
1630 std::ostringstream stalled;
1631
1632 executeInfo[0].instsBeingCommitted.reportData(insts);
1633 lsq.minorTrace();
1634 inputBuffer[0].minorTrace();
1635 scoreboard[0].minorTrace();
1636
1637 /* Report functional unit stalling in one string */
1638 unsigned int i = 0;
1639 while (i < numFuncUnits)
1640 {
1641 stalled << (funcUnits[i]->stalled ? '1' : 'E');
1642 i++;
1643 if (i != numFuncUnits)
1644 stalled << ',';
1645 }
1646
1647 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1648 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1649 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum,
1650 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0));
1651
1652 std::for_each(funcUnits.begin(), funcUnits.end(),
1653 std::mem_fun(&FUPipeline::minorTrace));
1654
1655 executeInfo[0].inFlightInsts->minorTrace();
1656 executeInfo[0].inFUMemInsts->minorTrace();
1657}
1658
1659inline ThreadID
1660Execute::getCommittingThread()
1661{
1662 std::vector<ThreadID> priority_list;
1663
1664 switch (cpu.threadPolicy) {
1665 case Enums::SingleThreaded:
1666 return 0;
1667 case Enums::RoundRobin:
1668 priority_list = cpu.roundRobinPriority(commitPriority);
1669 break;
1670 case Enums::Random:
1671 priority_list = cpu.randomPriority();
1672 break;
1673 default:
1674 panic("Invalid thread policy");
1675 }
1676
1677 for (auto tid : priority_list) {
1678 ExecuteThreadInfo &ex_info = executeInfo[tid];
| 1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/execute.hh"
41
42#include "arch/locked_mem.hh"
43#include "arch/registers.hh"
44#include "arch/utility.hh"
45#include "cpu/minor/cpu.hh"
46#include "cpu/minor/exec_context.hh"
47#include "cpu/minor/fetch1.hh"
48#include "cpu/minor/lsq.hh"
49#include "cpu/op_class.hh"
50#include "debug/Activity.hh"
51#include "debug/Branch.hh"
52#include "debug/Drain.hh"
53#include "debug/MinorExecute.hh"
54#include "debug/MinorInterrupt.hh"
55#include "debug/MinorMem.hh"
56#include "debug/MinorTrace.hh"
57#include "debug/PCEvent.hh"
58
59namespace Minor
60{
61
62Execute::Execute(const std::string &name_,
63 MinorCPU &cpu_,
64 MinorCPUParams ¶ms,
65 Latch<ForwardInstData>::Output inp_,
66 Latch<BranchData>::Input out_) :
67 Named(name_),
68 inp(inp_),
69 out(out_),
70 cpu(cpu_),
71 issueLimit(params.executeIssueLimit),
72 memoryIssueLimit(params.executeMemoryIssueLimit),
73 commitLimit(params.executeCommitLimit),
74 memoryCommitLimit(params.executeMemoryCommitLimit),
75 processMoreThanOneInput(params.executeCycleInput),
76 fuDescriptions(*params.executeFuncUnits),
77 numFuncUnits(fuDescriptions.funcUnits.size()),
78 setTraceTimeOnCommit(params.executeSetTraceTimeOnCommit),
79 setTraceTimeOnIssue(params.executeSetTraceTimeOnIssue),
80 allowEarlyMemIssue(params.executeAllowEarlyMemoryIssue),
81 noCostFUIndex(fuDescriptions.funcUnits.size() + 1),
82 lsq(name_ + ".lsq", name_ + ".dcache_port",
83 cpu_, *this,
84 params.executeMaxAccessesInMemory,
85 params.executeMemoryWidth,
86 params.executeLSQRequestsQueueSize,
87 params.executeLSQTransfersQueueSize,
88 params.executeLSQStoreBufferSize,
89 params.executeLSQMaxStoreBufferStoresPerCycle),
90 executeInfo(params.numThreads, ExecuteThreadInfo(params.executeCommitLimit)),
91 interruptPriority(0),
92 issuePriority(0),
93 commitPriority(0)
94{
95 if (commitLimit < 1) {
96 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
97 commitLimit);
98 }
99
100 if (issueLimit < 1) {
101 fatal("%s: executeCommitLimit must be >= 1 (%d)\n", name_,
102 issueLimit);
103 }
104
105 if (memoryIssueLimit < 1) {
106 fatal("%s: executeMemoryIssueLimit must be >= 1 (%d)\n", name_,
107 memoryIssueLimit);
108 }
109
110 if (memoryCommitLimit > commitLimit) {
111 fatal("%s: executeMemoryCommitLimit (%d) must be <="
112 " executeCommitLimit (%d)\n",
113 name_, memoryCommitLimit, commitLimit);
114 }
115
116 if (params.executeInputBufferSize < 1) {
117 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
118 params.executeInputBufferSize);
119 }
120
121 if (params.executeInputBufferSize < 1) {
122 fatal("%s: executeInputBufferSize must be >= 1 (%d)\n", name_,
123 params.executeInputBufferSize);
124 }
125
126 /* This should be large enough to count all the in-FU instructions
127 * which need to be accounted for in the inFlightInsts
128 * queue */
129 unsigned int total_slots = 0;
130
131 /* Make FUPipelines for each MinorFU */
132 for (unsigned int i = 0; i < numFuncUnits; i++) {
133 std::ostringstream fu_name;
134 MinorFU *fu_description = fuDescriptions.funcUnits[i];
135
136 /* Note the total number of instruction slots (for sizing
137 * the inFlightInst queue) and the maximum latency of any FU
138 * (for sizing the activity recorder) */
139 total_slots += fu_description->opLat;
140
141 fu_name << name_ << ".fu." << i;
142
143 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu);
144
145 funcUnits.push_back(fu);
146 }
147
148 /** Check that there is a functional unit for all operation classes */
149 for (int op_class = No_OpClass + 1; op_class < Num_OpClasses; op_class++) {
150 bool found_fu = false;
151 unsigned int fu_index = 0;
152
153 while (fu_index < numFuncUnits && !found_fu)
154 {
155 if (funcUnits[fu_index]->provides(
156 static_cast<OpClass>(op_class)))
157 {
158 found_fu = true;
159 }
160 fu_index++;
161 }
162
163 if (!found_fu) {
164 warn("No functional unit for OpClass %s\n",
165 Enums::OpClassStrings[op_class]);
166 }
167 }
168
169 /* Per-thread structures */
170 for (ThreadID tid = 0; tid < params.numThreads; tid++) {
171 std::string tid_str = std::to_string(tid);
172
173 /* Input Buffers */
174 inputBuffer.push_back(
175 InputBuffer<ForwardInstData>(
176 name_ + ".inputBuffer" + tid_str, "insts",
177 params.executeInputBufferSize));
178
179 /* Scoreboards */
180 scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
181
182 /* In-flight instruction records */
183 executeInfo[tid].inFlightInsts = new Queue<QueuedInst,
184 ReportTraitsAdaptor<QueuedInst> >(
185 name_ + ".inFlightInsts" + tid_str, "insts", total_slots);
186
187 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst,
188 ReportTraitsAdaptor<QueuedInst> >(
189 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots);
190 }
191}
192
193const ForwardInstData *
194Execute::getInput(ThreadID tid)
195{
196 /* Get a line from the inputBuffer to work with */
197 if (!inputBuffer[tid].empty()) {
198 const ForwardInstData &head = inputBuffer[tid].front();
199
200 return (head.isBubble() ? NULL : &(inputBuffer[tid].front()));
201 } else {
202 return NULL;
203 }
204}
205
206void
207Execute::popInput(ThreadID tid)
208{
209 if (!inputBuffer[tid].empty())
210 inputBuffer[tid].pop();
211
212 executeInfo[tid].inputIndex = 0;
213}
214
215void
216Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch)
217{
218 ThreadContext *thread = cpu.getContext(inst->id.threadId);
219 const TheISA::PCState &pc_before = inst->pc;
220 TheISA::PCState target = thread->pcState();
221
222 /* Force a branch for SerializeAfter/SquashAfter instructions
223 * at the end of micro-op sequence when we're not suspended */
224 bool force_branch = thread->status() != ThreadContext::Suspended &&
225 !inst->isFault() &&
226 inst->isLastOpInInst() &&
227 (inst->staticInst->isSerializeAfter() ||
228 inst->staticInst->isSquashAfter() ||
229 inst->staticInst->isIprAccess());
230
231 DPRINTF(Branch, "tryToBranch before: %s after: %s%s\n",
232 pc_before, target, (force_branch ? " (forcing)" : ""));
233
234 /* Will we change the PC to something other than the next instruction? */
235 bool must_branch = pc_before != target ||
236 fault != NoFault ||
237 force_branch;
238
239 /* The reason for the branch data we're about to generate, set below */
240 BranchData::Reason reason = BranchData::NoBranch;
241
242 if (fault == NoFault)
243 {
244 TheISA::advancePC(target, inst->staticInst);
245 thread->pcState(target);
246
247 DPRINTF(Branch, "Advancing current PC from: %s to: %s\n",
248 pc_before, target);
249 }
250
251 if (inst->predictedTaken && !force_branch) {
252 /* Predicted to branch */
253 if (!must_branch) {
254 /* No branch was taken, change stream to get us back to the
255 * intended PC value */
256 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x but"
257 " none happened inst: %s\n",
258 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
259
260 reason = BranchData::BadlyPredictedBranch;
261 } else if (inst->predictedTarget == target) {
262 /* Branch prediction got the right target, kill the branch and
263 * carry on.
264 * Note that this information to the branch predictor might get
265 * overwritten by a "real" branch during this cycle */
266 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x correctly"
267 " inst: %s\n",
268 inst->pc.instAddr(), inst->predictedTarget.instAddr(), *inst);
269
270 reason = BranchData::CorrectlyPredictedBranch;
271 } else {
272 /* Branch prediction got the wrong target */
273 DPRINTF(Branch, "Predicted a branch from 0x%x to 0x%x"
274 " but got the wrong target (actual: 0x%x) inst: %s\n",
275 inst->pc.instAddr(), inst->predictedTarget.instAddr(),
276 target.instAddr(), *inst);
277
278 reason = BranchData::BadlyPredictedBranchTarget;
279 }
280 } else if (must_branch) {
281 /* Unpredicted branch */
282 DPRINTF(Branch, "Unpredicted branch from 0x%x to 0x%x inst: %s\n",
283 inst->pc.instAddr(), target.instAddr(), *inst);
284
285 reason = BranchData::UnpredictedBranch;
286 } else {
287 /* No branch at all */
288 reason = BranchData::NoBranch;
289 }
290
291 updateBranchData(inst->id.threadId, reason, inst, target, branch);
292}
293
294void
295Execute::updateBranchData(
296 ThreadID tid,
297 BranchData::Reason reason,
298 MinorDynInstPtr inst, const TheISA::PCState &target,
299 BranchData &branch)
300{
301 if (reason != BranchData::NoBranch) {
302 /* Bump up the stream sequence number on a real branch*/
303 if (BranchData::isStreamChange(reason))
304 executeInfo[tid].streamSeqNum++;
305
306 /* Branches (even mis-predictions) don't change the predictionSeqNum,
307 * just the streamSeqNum */
308 branch = BranchData(reason, tid,
309 executeInfo[tid].streamSeqNum,
310 /* Maintaining predictionSeqNum if there's no inst is just a
311 * courtesy and looks better on minorview */
312 (inst->isBubble() ? executeInfo[tid].lastPredictionSeqNum
313 : inst->id.predictionSeqNum),
314 target, inst);
315
316 DPRINTF(Branch, "Branch data signalled: %s\n", branch);
317 }
318}
319
320void
321Execute::handleMemResponse(MinorDynInstPtr inst,
322 LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault)
323{
324 ThreadID thread_id = inst->id.threadId;
325 ThreadContext *thread = cpu.getContext(thread_id);
326
327 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
328
329 PacketPtr packet = response->packet;
330
331 bool is_load = inst->staticInst->isLoad();
332 bool is_store = inst->staticInst->isStore();
333 bool is_prefetch = inst->staticInst->isDataPrefetch();
334
335 /* If true, the trace's predicate value will be taken from the exec
336 * context predicate, otherwise, it will be set to false */
337 bool use_context_predicate = true;
338
339 if (response->fault != NoFault) {
340 /* Invoke memory faults. */
341 DPRINTF(MinorMem, "Completing fault from DTLB access: %s\n",
342 response->fault->name());
343
344 if (inst->staticInst->isPrefetch()) {
345 DPRINTF(MinorMem, "Not taking fault on prefetch: %s\n",
346 response->fault->name());
347
348 /* Don't assign to fault */
349 } else {
350 /* Take the fault raised during the TLB/memory access */
351 fault = response->fault;
352
353 fault->invoke(thread, inst->staticInst);
354 }
355 } else if (!packet) {
356 DPRINTF(MinorMem, "Completing failed request inst: %s\n",
357 *inst);
358 use_context_predicate = false;
359 } else if (packet->isError()) {
360 DPRINTF(MinorMem, "Trying to commit error response: %s\n",
361 *inst);
362
363 fatal("Received error response packet for inst: %s\n", *inst);
364 } else if (is_store || is_load || is_prefetch) {
365 assert(packet);
366
367 DPRINTF(MinorMem, "Memory response inst: %s addr: 0x%x size: %d\n",
368 *inst, packet->getAddr(), packet->getSize());
369
370 if (is_load && packet->getSize() > 0) {
371 DPRINTF(MinorMem, "Memory data[0]: 0x%x\n",
372 static_cast<unsigned int>(packet->getConstPtr<uint8_t>()[0]));
373 }
374
375 /* Complete the memory access instruction */
376 fault = inst->staticInst->completeAcc(packet, &context,
377 inst->traceData);
378
379 if (fault != NoFault) {
380 /* Invoke fault created by instruction completion */
381 DPRINTF(MinorMem, "Fault in memory completeAcc: %s\n",
382 fault->name());
383 fault->invoke(thread, inst->staticInst);
384 } else {
385 /* Stores need to be pushed into the store buffer to finish
386 * them off */
387 if (response->needsToBeSentToStoreBuffer())
388 lsq.sendStoreToStoreBuffer(response);
389 }
390 } else {
391 fatal("There should only ever be reads, "
392 "writes or faults at this point\n");
393 }
394
395 lsq.popResponse(response);
396
397 if (inst->traceData) {
398 inst->traceData->setPredicate((use_context_predicate ?
399 context.readPredicate() : false));
400 }
401
402 doInstCommitAccounting(inst);
403
404 /* Generate output to account for branches */
405 tryToBranch(inst, fault, branch);
406}
407
408bool
409Execute::isInterrupted(ThreadID thread_id) const
410{
411 return cpu.checkInterrupts(cpu.getContext(thread_id));
412}
413
414bool
415Execute::takeInterrupt(ThreadID thread_id, BranchData &branch)
416{
417 DPRINTF(MinorInterrupt, "Considering interrupt status from PC: %s\n",
418 cpu.getContext(thread_id)->pcState());
419
420 Fault interrupt = cpu.getInterruptController(thread_id)->getInterrupt
421 (cpu.getContext(thread_id));
422
423 if (interrupt != NoFault) {
424 /* The interrupt *must* set pcState */
425 cpu.getInterruptController(thread_id)->updateIntrInfo
426 (cpu.getContext(thread_id));
427 interrupt->invoke(cpu.getContext(thread_id));
428
429 assert(!lsq.accessesInFlight());
430
431 DPRINTF(MinorInterrupt, "Invoking interrupt: %s to PC: %s\n",
432 interrupt->name(), cpu.getContext(thread_id)->pcState());
433
434 /* Assume that an interrupt *must* cause a branch. Assert this? */
435
436 updateBranchData(thread_id, BranchData::Interrupt,
437 MinorDynInst::bubble(), cpu.getContext(thread_id)->pcState(),
438 branch);
439 }
440
441 return interrupt != NoFault;
442}
443
444bool
445Execute::executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
446 bool &passed_predicate, Fault &fault)
447{
448 bool issued = false;
449
450 /* Set to true if the mem op. is issued and sent to the mem system */
451 passed_predicate = false;
452
453 if (!lsq.canRequest()) {
454 /* Not acting on instruction yet as the memory
455 * queues are full */
456 issued = false;
457 } else {
458 ThreadContext *thread = cpu.getContext(inst->id.threadId);
459 TheISA::PCState old_pc = thread->pcState();
460
461 ExecContext context(cpu, *cpu.threads[inst->id.threadId],
462 *this, inst);
463
464 DPRINTF(MinorExecute, "Initiating memRef inst: %s\n", *inst);
465
466 Fault init_fault = inst->staticInst->initiateAcc(&context,
467 inst->traceData);
468
469 if (init_fault != NoFault) {
470 DPRINTF(MinorExecute, "Fault on memory inst: %s"
471 " initiateAcc: %s\n", *inst, init_fault->name());
472 fault = init_fault;
473 } else {
474 /* Only set this if the instruction passed its
475 * predicate */
476 passed_predicate = context.readPredicate();
477
478 /* Set predicate in tracing */
479 if (inst->traceData)
480 inst->traceData->setPredicate(passed_predicate);
481
482 /* If the instruction didn't pass its predicate (and so will not
483 * progress from here) Try to branch to correct and branch
484 * mis-prediction. */
485 if (!passed_predicate) {
486 /* Leave it up to commit to handle the fault */
487 lsq.pushFailedRequest(inst);
488 }
489 }
490
491 /* Restore thread PC */
492 thread->pcState(old_pc);
493 issued = true;
494 }
495
496 return issued;
497}
498
499/** Increment a cyclic buffer index for indices [0, cycle_size-1] */
500inline unsigned int
501cyclicIndexInc(unsigned int index, unsigned int cycle_size)
502{
503 unsigned int ret = index + 1;
504
505 if (ret == cycle_size)
506 ret = 0;
507
508 return ret;
509}
510
511/** Decrement a cyclic buffer index for indices [0, cycle_size-1] */
512inline unsigned int
513cyclicIndexDec(unsigned int index, unsigned int cycle_size)
514{
515 int ret = index - 1;
516
517 if (ret < 0)
518 ret = cycle_size - 1;
519
520 return ret;
521}
522
523unsigned int
524Execute::issue(ThreadID thread_id)
525{
526 const ForwardInstData *insts_in = getInput(thread_id);
527 ExecuteThreadInfo &thread = executeInfo[thread_id];
528
529 /* Early termination if we have no instructions */
530 if (!insts_in)
531 return 0;
532
533 /* Start from the first FU */
534 unsigned int fu_index = 0;
535
536 /* Remains true while instructions are still being issued. If any
537 * instruction fails to issue, this is set to false and we exit issue.
538 * This strictly enforces in-order issue. For other issue behaviours,
539 * a more complicated test in the outer while loop below is needed. */
540 bool issued = true;
541
542 /* Number of insts issues this cycle to check for issueLimit */
543 unsigned num_insts_issued = 0;
544
545 /* Number of memory ops issues this cycle to check for memoryIssueLimit */
546 unsigned num_mem_insts_issued = 0;
547
548 /* Number of instructions discarded this cycle in order to enforce a
549 * discardLimit. @todo, add that parameter? */
550 unsigned num_insts_discarded = 0;
551
552 do {
553 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex];
554 Fault fault = inst->fault;
555 bool discarded = false;
556 bool issued_mem_ref = false;
557
558 if (inst->isBubble()) {
559 /* Skip */
560 issued = true;
561 } else if (cpu.getContext(thread_id)->status() ==
562 ThreadContext::Suspended)
563 {
564 DPRINTF(MinorExecute, "Discarding inst: %s from suspended"
565 " thread\n", *inst);
566
567 issued = true;
568 discarded = true;
569 } else if (inst->id.streamSeqNum != thread.streamSeqNum) {
570 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
571 " state was unexpected, expected: %d\n",
572 *inst, thread.streamSeqNum);
573 issued = true;
574 discarded = true;
575 } else {
576 /* Try and issue an instruction into an FU, assume we didn't and
577 * fix that in the loop */
578 issued = false;
579
580 /* Try FU from 0 each instruction */
581 fu_index = 0;
582
583 /* Try and issue a single instruction stepping through the
584 * available FUs */
585 do {
586 FUPipeline *fu = funcUnits[fu_index];
587
588 DPRINTF(MinorExecute, "Trying to issue inst: %s to FU: %d\n",
589 *inst, fu_index);
590
591 /* Does the examined fu have the OpClass-related capability
592 * needed to execute this instruction? Faults can always
593 * issue to any FU but probably should just 'live' in the
594 * inFlightInsts queue rather than having an FU. */
595 bool fu_is_capable = (!inst->isFault() ?
596 fu->provides(inst->staticInst->opClass()) : true);
597
598 if (inst->isNoCostInst()) {
599 /* Issue free insts. to a fake numbered FU */
600 fu_index = noCostFUIndex;
601
602 /* And start the countdown on activity to allow
603 * this instruction to get to the end of its FU */
604 cpu.activityRecorder->activity();
605
606 /* Mark the destinations for this instruction as
607 * busy */
608 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
609 Cycles(0), cpu.getContext(thread_id), false);
610
611 DPRINTF(MinorExecute, "Issuing %s to %d\n", inst->id, noCostFUIndex);
612 inst->fuIndex = noCostFUIndex;
613 inst->extraCommitDelay = Cycles(0);
614 inst->extraCommitDelayExpr = NULL;
615
616 /* Push the instruction onto the inFlight queue so
617 * it can be committed in order */
618 QueuedInst fu_inst(inst);
619 thread.inFlightInsts->push(fu_inst);
620
621 issued = true;
622
623 } else if (!fu_is_capable || fu->alreadyPushed()) {
624 /* Skip */
625 if (!fu_is_capable) {
626 DPRINTF(MinorExecute, "Can't issue as FU: %d isn't"
627 " capable\n", fu_index);
628 } else {
629 DPRINTF(MinorExecute, "Can't issue as FU: %d is"
630 " already busy\n", fu_index);
631 }
632 } else if (fu->stalled) {
633 DPRINTF(MinorExecute, "Can't issue inst: %s into FU: %d,"
634 " it's stalled\n",
635 *inst, fu_index);
636 } else if (!fu->canInsert()) {
637 DPRINTF(MinorExecute, "Can't issue inst: %s to busy FU"
638 " for another: %d cycles\n",
639 *inst, fu->cyclesBeforeInsert());
640 } else {
641 MinorFUTiming *timing = (!inst->isFault() ?
642 fu->findTiming(inst->staticInst) : NULL);
643
644 const std::vector<Cycles> *src_latencies =
645 (timing ? &(timing->srcRegsRelativeLats)
646 : NULL);
647
648 const std::vector<bool> *cant_forward_from_fu_indices =
649 &(fu->cantForwardFromFUIndices);
650
651 if (timing && timing->suppress) {
652 DPRINTF(MinorExecute, "Can't issue inst: %s as extra"
653 " decoding is suppressing it\n",
654 *inst);
655 } else if (!scoreboard[thread_id].canInstIssue(inst,
656 src_latencies, cant_forward_from_fu_indices,
657 cpu.curCycle(), cpu.getContext(thread_id)))
658 {
659 DPRINTF(MinorExecute, "Can't issue inst: %s yet\n",
660 *inst);
661 } else {
662 /* Can insert the instruction into this FU */
663 DPRINTF(MinorExecute, "Issuing inst: %s"
664 " into FU %d\n", *inst,
665 fu_index);
666
667 Cycles extra_dest_retire_lat = Cycles(0);
668 TimingExpr *extra_dest_retire_lat_expr = NULL;
669 Cycles extra_assumed_lat = Cycles(0);
670
671 /* Add the extraCommitDelay and extraAssumeLat to
672 * the FU pipeline timings */
673 if (timing) {
674 extra_dest_retire_lat =
675 timing->extraCommitLat;
676 extra_dest_retire_lat_expr =
677 timing->extraCommitLatExpr;
678 extra_assumed_lat =
679 timing->extraAssumedLat;
680 }
681
682 issued_mem_ref = inst->isMemRef();
683
684 QueuedInst fu_inst(inst);
685
686 /* Decorate the inst with FU details */
687 inst->fuIndex = fu_index;
688 inst->extraCommitDelay = extra_dest_retire_lat;
689 inst->extraCommitDelayExpr =
690 extra_dest_retire_lat_expr;
691
692 if (issued_mem_ref) {
693 /* Remember which instruction this memory op
694 * depends on so that initiateAcc can be called
695 * early */
696 if (allowEarlyMemIssue) {
697 inst->instToWaitFor =
698 scoreboard[thread_id].execSeqNumToWaitFor(inst,
699 cpu.getContext(thread_id));
700
701 if (lsq.getLastMemBarrier(thread_id) >
702 inst->instToWaitFor)
703 {
704 DPRINTF(MinorExecute, "A barrier will"
705 " cause a delay in mem ref issue of"
706 " inst: %s until after inst"
707 " %d(exec)\n", *inst,
708 lsq.getLastMemBarrier(thread_id));
709
710 inst->instToWaitFor =
711 lsq.getLastMemBarrier(thread_id);
712 } else {
713 DPRINTF(MinorExecute, "Memory ref inst:"
714 " %s must wait for inst %d(exec)"
715 " before issuing\n",
716 *inst, inst->instToWaitFor);
717 }
718
719 inst->canEarlyIssue = true;
720 }
721 /* Also queue this instruction in the memory ref
722 * queue to ensure in-order issue to the LSQ */
723 DPRINTF(MinorExecute, "Pushing mem inst: %s\n",
724 *inst);
725 thread.inFUMemInsts->push(fu_inst);
726 }
727
728 /* Issue to FU */
729 fu->push(fu_inst);
730 /* And start the countdown on activity to allow
731 * this instruction to get to the end of its FU */
732 cpu.activityRecorder->activity();
733
734 /* Mark the destinations for this instruction as
735 * busy */
736 scoreboard[thread_id].markupInstDests(inst, cpu.curCycle() +
737 fu->description.opLat +
738 extra_dest_retire_lat +
739 extra_assumed_lat,
740 cpu.getContext(thread_id),
741 issued_mem_ref && extra_assumed_lat == Cycles(0));
742
743 /* Push the instruction onto the inFlight queue so
744 * it can be committed in order */
745 thread.inFlightInsts->push(fu_inst);
746
747 issued = true;
748 }
749 }
750
751 fu_index++;
752 } while (fu_index != numFuncUnits && !issued);
753
754 if (!issued)
755 DPRINTF(MinorExecute, "Didn't issue inst: %s\n", *inst);
756 }
757
758 if (issued) {
759 /* Generate MinorTrace's MinorInst lines. Do this at commit
760 * to allow better instruction annotation? */
761 if (DTRACE(MinorTrace) && !inst->isBubble())
762 inst->minorTraceInst(*this);
763
764 /* Mark up barriers in the LSQ */
765 if (!discarded && inst->isInst() &&
766 inst->staticInst->isMemBarrier())
767 {
768 DPRINTF(MinorMem, "Issuing memory barrier inst: %s\n", *inst);
769 lsq.issuedMemBarrierInst(inst);
770 }
771
772 if (inst->traceData && setTraceTimeOnIssue) {
773 inst->traceData->setWhen(curTick());
774 }
775
776 if (issued_mem_ref)
777 num_mem_insts_issued++;
778
779 if (discarded) {
780 num_insts_discarded++;
781 } else if (!inst->isBubble()) {
782 num_insts_issued++;
783
784 if (num_insts_issued == issueLimit)
785 DPRINTF(MinorExecute, "Reached inst issue limit\n");
786 }
787
788 thread.inputIndex++;
789 DPRINTF(MinorExecute, "Stepping to next inst inputIndex: %d\n",
790 thread.inputIndex);
791 }
792
793 /* Got to the end of a line */
794 if (thread.inputIndex == insts_in->width()) {
795 popInput(thread_id);
796 /* Set insts_in to null to force us to leave the surrounding
797 * loop */
798 insts_in = NULL;
799
800 if (processMoreThanOneInput) {
801 DPRINTF(MinorExecute, "Wrapping\n");
802 insts_in = getInput(thread_id);
803 }
804 }
805 } while (insts_in && thread.inputIndex < insts_in->width() &&
806 /* We still have instructions */
807 fu_index != numFuncUnits && /* Not visited all FUs */
808 issued && /* We've not yet failed to issue an instruction */
809 num_insts_issued != issueLimit && /* Still allowed to issue */
810 num_mem_insts_issued != memoryIssueLimit);
811
812 return num_insts_issued;
813}
814
815bool
816Execute::tryPCEvents(ThreadID thread_id)
817{
818 ThreadContext *thread = cpu.getContext(thread_id);
819 unsigned int num_pc_event_checks = 0;
820
821 /* Handle PC events on instructions */
822 Addr oldPC;
823 do {
824 oldPC = thread->instAddr();
825 cpu.system->pcEventQueue.service(thread);
826 num_pc_event_checks++;
827 } while (oldPC != thread->instAddr());
828
829 if (num_pc_event_checks > 1) {
830 DPRINTF(PCEvent, "Acting on PC Event to PC: %s\n",
831 thread->pcState());
832 }
833
834 return num_pc_event_checks > 1;
835}
836
837void
838Execute::doInstCommitAccounting(MinorDynInstPtr inst)
839{
840 assert(!inst->isFault());
841
842 MinorThread *thread = cpu.threads[inst->id.threadId];
843
844 /* Increment the many and various inst and op counts in the
845 * thread and system */
846 if (!inst->staticInst->isMicroop() || inst->staticInst->isLastMicroop())
847 {
848 thread->numInst++;
849 thread->numInsts++;
850 cpu.stats.numInsts++;
851 cpu.system->totalNumInsts++;
852
853 /* Act on events related to instruction counts */
854 cpu.comInstEventQueue[inst->id.threadId]->serviceEvents(thread->numInst);
855 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts);
856 }
857 thread->numOp++;
858 thread->numOps++;
859 cpu.stats.numOps++;
860 cpu.stats.committedInstType[inst->id.threadId]
861 [inst->staticInst->opClass()]++;
862
863 /* Set the CP SeqNum to the numOps commit number */
864 if (inst->traceData)
865 inst->traceData->setCPSeq(thread->numOp);
866
867 cpu.probeInstCommit(inst->staticInst);
868}
869
870bool
871Execute::commitInst(MinorDynInstPtr inst, bool early_memory_issue,
872 BranchData &branch, Fault &fault, bool &committed,
873 bool &completed_mem_issue)
874{
875 ThreadID thread_id = inst->id.threadId;
876 ThreadContext *thread = cpu.getContext(thread_id);
877
878 bool completed_inst = true;
879 fault = NoFault;
880
881 /* Is the thread for this instruction suspended? In that case, just
882 * stall as long as there are no pending interrupts */
883 if (thread->status() == ThreadContext::Suspended &&
884 !isInterrupted(thread_id))
885 {
886 panic("We should never hit the case where we try to commit from a "
887 "suspended thread as the streamSeqNum should not match");
888 } else if (inst->isFault()) {
889 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
890
891 DPRINTF(MinorExecute, "Fault inst reached Execute: %s\n",
892 inst->fault->name());
893
894 fault = inst->fault;
895 inst->fault->invoke(thread, NULL);
896
897 tryToBranch(inst, fault, branch);
898 } else if (inst->staticInst->isMemRef()) {
899 /* Memory accesses are executed in two parts:
900 * executeMemRefInst -- calculates the EA and issues the access
901 * to memory. This is done here.
902 * handleMemResponse -- handles the response packet, done by
903 * Execute::commit
904 *
905 * While the memory access is in its FU, the EA is being
906 * calculated. At the end of the FU, when it is ready to
907 * 'commit' (in this function), the access is presented to the
908 * memory queues. When a response comes back from memory,
909 * Execute::commit will commit it.
910 */
911 bool predicate_passed = false;
912 bool completed_mem_inst = executeMemRefInst(inst, branch,
913 predicate_passed, fault);
914
915 if (completed_mem_inst && fault != NoFault) {
916 if (early_memory_issue) {
917 DPRINTF(MinorExecute, "Fault in early executing inst: %s\n",
918 fault->name());
919 /* Don't execute the fault, just stall the instruction
920 * until it gets to the head of inFlightInsts */
921 inst->canEarlyIssue = false;
922 /* Not completed as we'll come here again to pick up
923 * the fault when we get to the end of the FU */
924 completed_inst = false;
925 } else {
926 DPRINTF(MinorExecute, "Fault in execute: %s\n",
927 fault->name());
928 fault->invoke(thread, NULL);
929
930 tryToBranch(inst, fault, branch);
931 completed_inst = true;
932 }
933 } else {
934 completed_inst = completed_mem_inst;
935 }
936 completed_mem_issue = completed_inst;
937 } else if (inst->isInst() && inst->staticInst->isMemBarrier() &&
938 !lsq.canPushIntoStoreBuffer())
939 {
940 DPRINTF(MinorExecute, "Can't commit data barrier inst: %s yet as"
941 " there isn't space in the store buffer\n", *inst);
942
943 completed_inst = false;
944 } else if (inst->isInst() && inst->staticInst->isQuiesce()
945 && !branch.isBubble()){
946 /* This instruction can suspend, need to be able to communicate
947 * backwards, so no other branches may evaluate this cycle*/
948 completed_inst = false;
949 } else {
950 ExecContext context(cpu, *cpu.threads[thread_id], *this, inst);
951
952 DPRINTF(MinorExecute, "Committing inst: %s\n", *inst);
953
954 fault = inst->staticInst->execute(&context,
955 inst->traceData);
956
957 /* Set the predicate for tracing and dump */
958 if (inst->traceData)
959 inst->traceData->setPredicate(context.readPredicate());
960
961 committed = true;
962
963 if (fault != NoFault) {
964 DPRINTF(MinorExecute, "Fault in execute of inst: %s fault: %s\n",
965 *inst, fault->name());
966 fault->invoke(thread, inst->staticInst);
967 }
968
969 doInstCommitAccounting(inst);
970 tryToBranch(inst, fault, branch);
971 }
972
973 if (completed_inst) {
974 /* Keep a copy of this instruction's predictionSeqNum just in case
975 * we need to issue a branch without an instruction (such as an
976 * interrupt) */
977 executeInfo[thread_id].lastPredictionSeqNum = inst->id.predictionSeqNum;
978
979 /* Check to see if this instruction suspended the current thread. */
980 if (!inst->isFault() &&
981 thread->status() == ThreadContext::Suspended &&
982 branch.isBubble() && /* It didn't branch too */
983 !isInterrupted(thread_id)) /* Don't suspend if we have
984 interrupts */
985 {
986 TheISA::PCState resume_pc = cpu.getContext(thread_id)->pcState();
987
988 assert(resume_pc.microPC() == 0);
989
990 DPRINTF(MinorInterrupt, "Suspending thread: %d from Execute"
991 " inst: %s\n", thread_id, *inst);
992
993 cpu.stats.numFetchSuspends++;
994
995 updateBranchData(thread_id, BranchData::SuspendThread, inst,
996 resume_pc, branch);
997 }
998 }
999
1000 return completed_inst;
1001}
1002
1003void
1004Execute::commit(ThreadID thread_id, bool only_commit_microops, bool discard,
1005 BranchData &branch)
1006{
1007 Fault fault = NoFault;
1008 Cycles now = cpu.curCycle();
1009 ExecuteThreadInfo &ex_info = executeInfo[thread_id];
1010
1011 /**
1012 * Try and execute as many instructions from the end of FU pipelines as
1013 * possible. This *doesn't* include actually advancing the pipelines.
1014 *
1015 * We do this by looping on the front of the inFlightInsts queue for as
1016 * long as we can find the desired instruction at the end of the
1017 * functional unit it was issued to without seeing a branch or a fault.
1018 * In this function, these terms are used:
1019 * complete -- The instruction has finished its passage through
1020 * its functional unit and its fate has been decided
1021 * (committed, discarded, issued to the memory system)
1022 * commit -- The instruction is complete(d), not discarded and has
1023 * its effects applied to the CPU state
1024 * discard(ed) -- The instruction is complete but not committed
1025 * as its streamSeqNum disagrees with the current
1026 * Execute::streamSeqNum
1027 *
1028 * Commits are also possible from two other places:
1029 *
1030 * 1) Responses returning from the LSQ
1031 * 2) Mem ops issued to the LSQ ('committed' from the FUs) earlier
1032 * than their position in the inFlightInsts queue, but after all
1033 * their dependencies are resolved.
1034 */
1035
1036 /* Has an instruction been completed? Once this becomes false, we stop
1037 * trying to complete instructions. */
1038 bool completed_inst = true;
1039
1040 /* Number of insts committed this cycle to check against commitLimit */
1041 unsigned int num_insts_committed = 0;
1042
1043 /* Number of memory access instructions committed to check against
1044 * memCommitLimit */
1045 unsigned int num_mem_refs_committed = 0;
1046
1047 if (only_commit_microops && !ex_info.inFlightInsts->empty()) {
1048 DPRINTF(MinorInterrupt, "Only commit microops %s %d\n",
1049 *(ex_info.inFlightInsts->front().inst),
1050 ex_info.lastCommitWasEndOfMacroop);
1051 }
1052
1053 while (!ex_info.inFlightInsts->empty() && /* Some more instructions to process */
1054 !branch.isStreamChange() && /* No real branch */
1055 fault == NoFault && /* No faults */
1056 completed_inst && /* Still finding instructions to execute */
1057 num_insts_committed != commitLimit && /* Not reached commit limit */
1058 cpu.getContext(thread_id)->status() != ThreadContext::Suspended
1059 )
1060 {
1061 if (only_commit_microops) {
1062 DPRINTF(MinorInterrupt, "Committing tail of insts before"
1063 " interrupt: %s\n",
1064 *(ex_info.inFlightInsts->front().inst));
1065 }
1066
1067 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1068
1069 InstSeqNum head_exec_seq_num =
1070 head_inflight_inst->inst->id.execSeqNum;
1071
1072 /* The instruction we actually process if completed_inst
1073 * remains true to the end of the loop body.
1074 * Start by considering the the head of the in flight insts queue */
1075 MinorDynInstPtr inst = head_inflight_inst->inst;
1076
1077 bool committed_inst = false;
1078 bool discard_inst = false;
1079 bool completed_mem_ref = false;
1080 bool issued_mem_ref = false;
1081 bool early_memory_issue = false;
1082
1083 /* Must set this again to go around the loop */
1084 completed_inst = false;
1085
1086 /* If we're just completing a macroop before an interrupt or drain,
1087 * can we stil commit another microop (rather than a memory response)
1088 * without crosing into the next full instruction? */
1089 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1090 !(only_commit_microops && ex_info.lastCommitWasEndOfMacroop);
1091
1092 /* Can we find a mem response for this inst */
1093 LSQ::LSQRequestPtr mem_response =
1094 (inst->inLSQ ? lsq.findResponse(inst) : NULL);
1095
1096 DPRINTF(MinorExecute, "Trying to commit canCommitInsts: %d\n",
1097 can_commit_insts);
1098
1099 /* Test for PC events after every instruction */
1100 if (isInbetweenInsts(thread_id) && tryPCEvents(thread_id)) {
1101 ThreadContext *thread = cpu.getContext(thread_id);
1102
1103 /* Branch as there was a change in PC */
1104 updateBranchData(thread_id, BranchData::UnpredictedBranch,
1105 MinorDynInst::bubble(), thread->pcState(), branch);
1106 } else if (mem_response &&
1107 num_mem_refs_committed < memoryCommitLimit)
1108 {
1109 /* Try to commit from the memory responses next */
1110 discard_inst = inst->id.streamSeqNum !=
1111 ex_info.streamSeqNum || discard;
1112
1113 DPRINTF(MinorExecute, "Trying to commit mem response: %s\n",
1114 *inst);
1115
1116 /* Complete or discard the response */
1117 if (discard_inst) {
1118 DPRINTF(MinorExecute, "Discarding mem inst: %s as its"
1119 " stream state was unexpected, expected: %d\n",
1120 *inst, ex_info.streamSeqNum);
1121
1122 lsq.popResponse(mem_response);
1123 } else {
1124 handleMemResponse(inst, mem_response, branch, fault);
1125 committed_inst = true;
1126 }
1127
1128 completed_mem_ref = true;
1129 completed_inst = true;
1130 } else if (can_commit_insts) {
1131 /* If true, this instruction will, subject to timing tweaks,
1132 * be considered for completion. try_to_commit flattens
1133 * the `if' tree a bit and allows other tests for inst
1134 * commit to be inserted here. */
1135 bool try_to_commit = false;
1136
1137 /* Try and issue memory ops early if they:
1138 * - Can push a request into the LSQ
1139 * - Have reached the end of their FUs
1140 * - Have had all their dependencies satisfied
1141 * - Are from the right stream
1142 *
1143 * For any other case, leave it to the normal instruction
1144 * issue below to handle them.
1145 */
1146 if (!ex_info.inFUMemInsts->empty() && lsq.canRequest()) {
1147 DPRINTF(MinorExecute, "Trying to commit from mem FUs\n");
1148
1149 const MinorDynInstPtr head_mem_ref_inst =
1150 ex_info.inFUMemInsts->front().inst;
1151 FUPipeline *fu = funcUnits[head_mem_ref_inst->fuIndex];
1152 const MinorDynInstPtr &fu_inst = fu->front().inst;
1153
1154 /* Use this, possibly out of order, inst as the one
1155 * to 'commit'/send to the LSQ */
1156 if (!fu_inst->isBubble() &&
1157 !fu_inst->inLSQ &&
1158 fu_inst->canEarlyIssue &&
1159 ex_info.streamSeqNum == fu_inst->id.streamSeqNum &&
1160 head_exec_seq_num > fu_inst->instToWaitFor)
1161 {
1162 DPRINTF(MinorExecute, "Issuing mem ref early"
1163 " inst: %s instToWaitFor: %d\n",
1164 *(fu_inst), fu_inst->instToWaitFor);
1165
1166 inst = fu_inst;
1167 try_to_commit = true;
1168 early_memory_issue = true;
1169 completed_inst = true;
1170 }
1171 }
1172
1173 /* Try and commit FU-less insts */
1174 if (!completed_inst && inst->isNoCostInst()) {
1175 DPRINTF(MinorExecute, "Committing no cost inst: %s", *inst);
1176
1177 try_to_commit = true;
1178 completed_inst = true;
1179 }
1180
1181 /* Try to issue from the ends of FUs and the inFlightInsts
1182 * queue */
1183 if (!completed_inst && !inst->inLSQ) {
1184 DPRINTF(MinorExecute, "Trying to commit from FUs\n");
1185
1186 /* Try to commit from a functional unit */
1187 /* Is the head inst of the expected inst's FU actually the
1188 * expected inst? */
1189 QueuedInst &fu_inst =
1190 funcUnits[inst->fuIndex]->front();
1191 InstSeqNum fu_inst_seq_num = fu_inst.inst->id.execSeqNum;
1192
1193 if (fu_inst.inst->isBubble()) {
1194 /* No instruction ready */
1195 completed_inst = false;
1196 } else if (fu_inst_seq_num != head_exec_seq_num) {
1197 /* Past instruction: we must have already executed it
1198 * in the same cycle and so the head inst isn't
1199 * actually at the end of its pipeline
1200 * Future instruction: handled above and only for
1201 * mem refs on their way to the LSQ */
1202 } else if (fu_inst.inst->id == inst->id) {
1203 /* All instructions can be committed if they have the
1204 * right execSeqNum and there are no in-flight
1205 * mem insts before us */
1206 try_to_commit = true;
1207 completed_inst = true;
1208 }
1209 }
1210
1211 if (try_to_commit) {
1212 discard_inst = inst->id.streamSeqNum !=
1213 ex_info.streamSeqNum || discard;
1214
1215 /* Is this instruction discardable as its streamSeqNum
1216 * doesn't match? */
1217 if (!discard_inst) {
1218 /* Try to commit or discard a non-memory instruction.
1219 * Memory ops are actually 'committed' from this FUs
1220 * and 'issued' into the memory system so we need to
1221 * account for them later (commit_was_mem_issue gets
1222 * set) */
1223 if (inst->extraCommitDelayExpr) {
1224 DPRINTF(MinorExecute, "Evaluating expression for"
1225 " extra commit delay inst: %s\n", *inst);
1226
1227 ThreadContext *thread = cpu.getContext(thread_id);
1228
1229 TimingExprEvalContext context(inst->staticInst,
1230 thread, NULL);
1231
1232 uint64_t extra_delay = inst->extraCommitDelayExpr->
1233 eval(context);
1234
1235 DPRINTF(MinorExecute, "Extra commit delay expr"
1236 " result: %d\n", extra_delay);
1237
1238 if (extra_delay < 128) {
1239 inst->extraCommitDelay += Cycles(extra_delay);
1240 } else {
1241 DPRINTF(MinorExecute, "Extra commit delay was"
1242 " very long: %d\n", extra_delay);
1243 }
1244 inst->extraCommitDelayExpr = NULL;
1245 }
1246
1247 /* Move the extraCommitDelay from the instruction
1248 * into the minimumCommitCycle */
1249 if (inst->extraCommitDelay != Cycles(0)) {
1250 inst->minimumCommitCycle = cpu.curCycle() +
1251 inst->extraCommitDelay;
1252 inst->extraCommitDelay = Cycles(0);
1253 }
1254
1255 /* @todo Think about making lastMemBarrier be
1256 * MAX_UINT_64 to avoid using 0 as a marker value */
1257 if (!inst->isFault() && inst->isMemRef() &&
1258 lsq.getLastMemBarrier(thread_id) <
1259 inst->id.execSeqNum &&
1260 lsq.getLastMemBarrier(thread_id) != 0)
1261 {
1262 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1263 " as there are incomplete barriers in flight\n",
1264 *inst);
1265 completed_inst = false;
1266 } else if (inst->minimumCommitCycle > now) {
1267 DPRINTF(MinorExecute, "Not committing inst: %s yet"
1268 " as it wants to be stalled for %d more cycles\n",
1269 *inst, inst->minimumCommitCycle - now);
1270 completed_inst = false;
1271 } else {
1272 completed_inst = commitInst(inst,
1273 early_memory_issue, branch, fault,
1274 committed_inst, issued_mem_ref);
1275 }
1276 } else {
1277 /* Discard instruction */
1278 completed_inst = true;
1279 }
1280
1281 if (completed_inst) {
1282 /* Allow the pipeline to advance. If the FU head
1283 * instruction wasn't the inFlightInsts head
1284 * but had already been committed, it would have
1285 * unstalled the pipeline before here */
1286 if (inst->fuIndex != noCostFUIndex) {
1287 DPRINTF(MinorExecute, "Unstalling %d for inst %s\n", inst->fuIndex, inst->id);
1288 funcUnits[inst->fuIndex]->stalled = false;
1289 }
1290 }
1291 }
1292 } else {
1293 DPRINTF(MinorExecute, "No instructions to commit\n");
1294 completed_inst = false;
1295 }
1296
1297 /* All discardable instructions must also be 'completed' by now */
1298 assert(!(discard_inst && !completed_inst));
1299
1300 /* Instruction committed but was discarded due to streamSeqNum
1301 * mismatch */
1302 if (discard_inst) {
1303 DPRINTF(MinorExecute, "Discarding inst: %s as its stream"
1304 " state was unexpected, expected: %d\n",
1305 *inst, ex_info.streamSeqNum);
1306
1307 if (fault == NoFault)
1308 cpu.stats.numDiscardedOps++;
1309 }
1310
1311 /* Mark the mem inst as being in the LSQ */
1312 if (issued_mem_ref) {
1313 inst->fuIndex = 0;
1314 inst->inLSQ = true;
1315 }
1316
1317 /* Pop issued (to LSQ) and discarded mem refs from the inFUMemInsts
1318 * as they've *definitely* exited the FUs */
1319 if (completed_inst && inst->isMemRef()) {
1320 /* The MemRef could have been discarded from the FU or the memory
1321 * queue, so just check an FU instruction */
1322 if (!ex_info.inFUMemInsts->empty() &&
1323 ex_info.inFUMemInsts->front().inst == inst)
1324 {
1325 ex_info.inFUMemInsts->pop();
1326 }
1327 }
1328
1329 if (completed_inst && !(issued_mem_ref && fault == NoFault)) {
1330 /* Note that this includes discarded insts */
1331 DPRINTF(MinorExecute, "Completed inst: %s\n", *inst);
1332
1333 /* Got to the end of a full instruction? */
1334 ex_info.lastCommitWasEndOfMacroop = inst->isFault() ||
1335 inst->isLastOpInInst();
1336
1337 /* lastPredictionSeqNum is kept as a convenience to prevent its
1338 * value from changing too much on the minorview display */
1339 ex_info.lastPredictionSeqNum = inst->id.predictionSeqNum;
1340
1341 /* Finished with the inst, remove it from the inst queue and
1342 * clear its dependencies */
1343 ex_info.inFlightInsts->pop();
1344
1345 /* Complete barriers in the LSQ/move to store buffer */
1346 if (inst->isInst() && inst->staticInst->isMemBarrier()) {
1347 DPRINTF(MinorMem, "Completing memory barrier"
1348 " inst: %s committed: %d\n", *inst, committed_inst);
1349 lsq.completeMemBarrierInst(inst, committed_inst);
1350 }
1351
1352 scoreboard[thread_id].clearInstDests(inst, inst->isMemRef());
1353 }
1354
1355 /* Handle per-cycle instruction counting */
1356 if (committed_inst) {
1357 bool is_no_cost_inst = inst->isNoCostInst();
1358
1359 /* Don't show no cost instructions as having taken a commit
1360 * slot */
1361 if (DTRACE(MinorTrace) && !is_no_cost_inst)
1362 ex_info.instsBeingCommitted.insts[num_insts_committed] = inst;
1363
1364 if (!is_no_cost_inst)
1365 num_insts_committed++;
1366
1367 if (num_insts_committed == commitLimit)
1368 DPRINTF(MinorExecute, "Reached inst commit limit\n");
1369
1370 /* Re-set the time of the instruction if that's required for
1371 * tracing */
1372 if (inst->traceData) {
1373 if (setTraceTimeOnCommit)
1374 inst->traceData->setWhen(curTick());
1375 inst->traceData->dump();
1376 }
1377
1378 if (completed_mem_ref)
1379 num_mem_refs_committed++;
1380
1381 if (num_mem_refs_committed == memoryCommitLimit)
1382 DPRINTF(MinorExecute, "Reached mem ref commit limit\n");
1383 }
1384 }
1385}
1386
1387bool
1388Execute::isInbetweenInsts(ThreadID thread_id) const
1389{
1390 return executeInfo[thread_id].lastCommitWasEndOfMacroop &&
1391 !lsq.accessesInFlight();
1392}
1393
1394void
1395Execute::evaluate()
1396{
1397 if (!inp.outputWire->isBubble())
1398 inputBuffer[inp.outputWire->threadId].setTail(*inp.outputWire);
1399
1400 BranchData &branch = *out.inputWire;
1401
1402 unsigned int num_issued = 0;
1403
1404 /* Do all the cycle-wise activities for dcachePort here to potentially
1405 * free up input spaces in the LSQ's requests queue */
1406 lsq.step();
1407
1408 /* Check interrupts first. Will halt commit if interrupt found */
1409 bool interrupted = false;
1410 ThreadID interrupt_tid = checkInterrupts(branch, interrupted);
1411
1412 if (interrupt_tid != InvalidThreadID) {
1413 /* Signalling an interrupt this cycle, not issuing/committing from
1414 * any other threads */
1415 } else if (!branch.isBubble()) {
1416 /* It's important that this is here to carry Fetch1 wakeups to Fetch1
1417 * without overwriting them */
1418 DPRINTF(MinorInterrupt, "Execute skipping a cycle to allow old"
1419 " branch to complete\n");
1420 } else {
1421 ThreadID commit_tid = getCommittingThread();
1422
1423 if (commit_tid != InvalidThreadID) {
1424 ExecuteThreadInfo& commit_info = executeInfo[commit_tid];
1425
1426 DPRINTF(MinorExecute, "Attempting to commit [tid:%d]\n",
1427 commit_tid);
1428 /* commit can set stalled flags observable to issue and so *must* be
1429 * called first */
1430 if (commit_info.drainState != NotDraining) {
1431 if (commit_info.drainState == DrainCurrentInst) {
1432 /* Commit only micro-ops, don't kill anything else */
1433 commit(commit_tid, true, false, branch);
1434
1435 if (isInbetweenInsts(commit_tid))
1436 setDrainState(commit_tid, DrainHaltFetch);
1437
1438 /* Discard any generated branch */
1439 branch = BranchData::bubble();
1440 } else if (commit_info.drainState == DrainAllInsts) {
1441 /* Kill all instructions */
1442 while (getInput(commit_tid))
1443 popInput(commit_tid);
1444 commit(commit_tid, false, true, branch);
1445 }
1446 } else {
1447 /* Commit micro-ops only if interrupted. Otherwise, commit
1448 * anything you like */
1449 DPRINTF(MinorExecute, "Committing micro-ops for interrupt[tid:%d]\n",
1450 commit_tid);
1451 bool only_commit_microops = interrupted &&
1452 hasInterrupt(commit_tid);
1453 commit(commit_tid, only_commit_microops, false, branch);
1454 }
1455
1456 /* Halt fetch, but don't do it until we have the current instruction in
1457 * the bag */
1458 if (commit_info.drainState == DrainHaltFetch) {
1459 updateBranchData(commit_tid, BranchData::HaltFetch,
1460 MinorDynInst::bubble(), TheISA::PCState(0), branch);
1461
1462 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1463 setDrainState(commit_tid, DrainAllInsts);
1464 }
1465 }
1466 ThreadID issue_tid = getIssuingThread();
1467 /* This will issue merrily even when interrupted in the sure and
1468 * certain knowledge that the interrupt with change the stream */
1469 if (issue_tid != InvalidThreadID) {
1470 DPRINTF(MinorExecute, "Attempting to issue [tid:%d]\n",
1471 issue_tid);
1472 num_issued = issue(issue_tid);
1473 }
1474
1475 }
1476
1477 /* Run logic to step functional units + decide if we are active on the next
1478 * clock cycle */
1479 std::vector<MinorDynInstPtr> next_issuable_insts;
1480 bool can_issue_next = false;
1481
1482 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {
1483 /* Find the next issuable instruction for each thread and see if it can
1484 be issued */
1485 if (getInput(tid)) {
1486 unsigned int input_index = executeInfo[tid].inputIndex;
1487 MinorDynInstPtr inst = getInput(tid)->insts[input_index];
1488 if (inst->isFault()) {
1489 can_issue_next = true;
1490 } else if (!inst->isBubble()) {
1491 next_issuable_insts.push_back(inst);
1492 }
1493 }
1494 }
1495
1496 bool becoming_stalled = true;
1497
1498 /* Advance the pipelines and note whether they still need to be
1499 * advanced */
1500 for (unsigned int i = 0; i < numFuncUnits; i++) {
1501 FUPipeline *fu = funcUnits[i];
1502 fu->advance();
1503
1504 /* If we need to tick again, the pipeline will have been left or set
1505 * to be unstalled */
1506 if (fu->occupancy !=0 && !fu->stalled)
1507 becoming_stalled = false;
1508
1509 /* Could we possibly issue the next instruction from any thread?
1510 * This is quite an expensive test and is only used to determine
1511 * if the CPU should remain active, only run it if we aren't sure
1512 * we are active next cycle yet */
1513 for (auto inst : next_issuable_insts) {
1514 if (!fu->stalled && fu->provides(inst->staticInst->opClass()) &&
1515 scoreboard[inst->id.threadId].canInstIssue(inst,
1516 NULL, NULL, cpu.curCycle() + Cycles(1),
1517 cpu.getContext(inst->id.threadId))) {
1518 can_issue_next = true;
1519 break;
1520 }
1521 }
1522 }
1523
1524 bool head_inst_might_commit = false;
1525
1526 /* Could the head in flight insts be committed */
1527 for (auto const &info : executeInfo) {
1528 if (!info.inFlightInsts->empty()) {
1529 const QueuedInst &head_inst = info.inFlightInsts->front();
1530
1531 if (head_inst.inst->isNoCostInst()) {
1532 head_inst_might_commit = true;
1533 } else {
1534 FUPipeline *fu = funcUnits[head_inst.inst->fuIndex];
1535 if ((fu->stalled &&
1536 fu->front().inst->id == head_inst.inst->id) ||
1537 lsq.findResponse(head_inst.inst))
1538 {
1539 head_inst_might_commit = true;
1540 break;
1541 }
1542 }
1543 }
1544 }
1545
1546 DPRINTF(Activity, "Need to tick num issued insts: %s%s%s%s%s%s\n",
1547 (num_issued != 0 ? " (issued some insts)" : ""),
1548 (becoming_stalled ? "(becoming stalled)" : "(not becoming stalled)"),
1549 (can_issue_next ? " (can issued next inst)" : ""),
1550 (head_inst_might_commit ? "(head inst might commit)" : ""),
1551 (lsq.needsToTick() ? " (LSQ needs to tick)" : ""),
1552 (interrupted ? " (interrupted)" : ""));
1553
1554 bool need_to_tick =
1555 num_issued != 0 || /* Issued some insts this cycle */
1556 !becoming_stalled || /* Some FU pipelines can still move */
1557 can_issue_next || /* Can still issue a new inst */
1558 head_inst_might_commit || /* Could possible commit the next inst */
1559 lsq.needsToTick() || /* Must step the dcache port */
1560 interrupted; /* There are pending interrupts */
1561
1562 if (!need_to_tick) {
1563 DPRINTF(Activity, "The next cycle might be skippable as there are no"
1564 " advanceable FUs\n");
1565 }
1566
1567 /* Wake up if we need to tick again */
1568 if (need_to_tick)
1569 cpu.wakeupOnEvent(Pipeline::ExecuteStageId);
1570
1571 /* Note activity of following buffer */
1572 if (!branch.isBubble())
1573 cpu.activityRecorder->activity();
1574
1575 /* Make sure the input (if any left) is pushed */
1576 if (!inp.outputWire->isBubble())
1577 inputBuffer[inp.outputWire->threadId].pushTail();
1578}
1579
1580ThreadID
1581Execute::checkInterrupts(BranchData& branch, bool& interrupted)
1582{
1583 ThreadID tid = interruptPriority;
1584 /* Evaluate interrupts in round-robin based upon service */
1585 do {
1586 /* Has an interrupt been signalled? This may not be acted on
1587 * straighaway so this is different from took_interrupt */
1588 bool thread_interrupted = false;
1589
1590 if (FullSystem && cpu.getInterruptController(tid)) {
1591 /* This is here because it seems that after drainResume the
1592 * interrupt controller isn't always set */
1593 thread_interrupted = executeInfo[tid].drainState == NotDraining &&
1594 isInterrupted(tid);
1595 interrupted = interrupted || thread_interrupted;
1596 } else {
1597 DPRINTF(MinorInterrupt, "No interrupt controller\n");
1598 }
1599 DPRINTF(MinorInterrupt, "[tid:%d] thread_interrupted?=%d isInbetweenInsts?=%d\n",
1600 tid, thread_interrupted, isInbetweenInsts(tid));
1601 /* Act on interrupts */
1602 if (thread_interrupted && isInbetweenInsts(tid)) {
1603 if (takeInterrupt(tid, branch)) {
1604 interruptPriority = tid;
1605 return tid;
1606 }
1607 } else {
1608 tid = (tid + 1) % cpu.numThreads;
1609 }
1610 } while (tid != interruptPriority);
1611
1612 return InvalidThreadID;
1613}
1614
1615bool
1616Execute::hasInterrupt(ThreadID thread_id)
1617{
1618 if (FullSystem && cpu.getInterruptController(thread_id)) {
1619 return executeInfo[thread_id].drainState == NotDraining &&
1620 isInterrupted(thread_id);
1621 }
1622
1623 return false;
1624}
1625
1626void
1627Execute::minorTrace() const
1628{
1629 std::ostringstream insts;
1630 std::ostringstream stalled;
1631
1632 executeInfo[0].instsBeingCommitted.reportData(insts);
1633 lsq.minorTrace();
1634 inputBuffer[0].minorTrace();
1635 scoreboard[0].minorTrace();
1636
1637 /* Report functional unit stalling in one string */
1638 unsigned int i = 0;
1639 while (i < numFuncUnits)
1640 {
1641 stalled << (funcUnits[i]->stalled ? '1' : 'E');
1642 i++;
1643 if (i != numFuncUnits)
1644 stalled << ',';
1645 }
1646
1647 MINORTRACE("insts=%s inputIndex=%d streamSeqNum=%d"
1648 " stalled=%s drainState=%d isInbetweenInsts=%d\n",
1649 insts.str(), executeInfo[0].inputIndex, executeInfo[0].streamSeqNum,
1650 stalled.str(), executeInfo[0].drainState, isInbetweenInsts(0));
1651
1652 std::for_each(funcUnits.begin(), funcUnits.end(),
1653 std::mem_fun(&FUPipeline::minorTrace));
1654
1655 executeInfo[0].inFlightInsts->minorTrace();
1656 executeInfo[0].inFUMemInsts->minorTrace();
1657}
1658
1659inline ThreadID
1660Execute::getCommittingThread()
1661{
1662 std::vector<ThreadID> priority_list;
1663
1664 switch (cpu.threadPolicy) {
1665 case Enums::SingleThreaded:
1666 return 0;
1667 case Enums::RoundRobin:
1668 priority_list = cpu.roundRobinPriority(commitPriority);
1669 break;
1670 case Enums::Random:
1671 priority_list = cpu.randomPriority();
1672 break;
1673 default:
1674 panic("Invalid thread policy");
1675 }
1676
1677 for (auto tid : priority_list) {
1678 ExecuteThreadInfo &ex_info = executeInfo[tid];
|