1/*
2 * Copyright (c) 2013-2014,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1678 priority_list = cpu.randomPriority();
1679 break;
1680 default:
1681 panic("Invalid thread policy");
1682 }
1683
1684 for (auto tid : priority_list) {
1685 ExecuteThreadInfo &ex_info = executeInfo[tid];
1686
1687 bool is_thread_active =
1688 cpu.getContext(tid)->status() == ThreadContext::Active;
1689 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1690 is_thread_active;
1691
1692 if (can_commit_insts) {
1693 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1694 MinorDynInstPtr inst = head_inflight_inst->inst;
1695
1696 can_commit_insts = can_commit_insts &&
1697 (!inst->inLSQ || (lsq.findResponse(inst) != NULL));
1698
1699 if (!inst->inLSQ) {

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1749 case Enums::Random:
1750 priority_list = cpu.randomPriority();
1751 break;
1752 default:
1753 panic("Invalid thread scheduling policy.");
1754 }
1755
1756 for (auto tid : priority_list) {
1757 if (cpu.getContext(tid)->status() == ThreadContext::Active &&
1758 getInput(tid)) {
1759 issuePriority = tid;
1760 return tid;
1761 }
1762 }
1763
1764 return InvalidThreadID;
1765}
1766

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