1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1671 priority_list = cpu.randomPriority();
1672 break;
1673 default:
1674 panic("Invalid thread policy");
1675 }
1676
1677 for (auto tid : priority_list) {
1678 ExecuteThreadInfo &ex_info = executeInfo[tid];
1679 bool can_commit_insts = !ex_info.inFlightInsts->empty();
1680 if (can_commit_insts) {
1681 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1682 MinorDynInstPtr inst = head_inflight_inst->inst;
1683
1684 can_commit_insts = can_commit_insts &&
1685 (!inst->inLSQ || (lsq.findResponse(inst) != NULL));
1686
1687 if (!inst->inLSQ) {

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1737 case Enums::Random:
1738 priority_list = cpu.randomPriority();
1739 break;
1740 default:
1741 panic("Invalid thread scheduling policy.");
1742 }
1743
1744 for (auto tid : priority_list) {
1745 if (getInput(tid)) {
1746 issuePriority = tid;
1747 return tid;
1748 }
1749 }
1750
1751 return InvalidThreadID;
1752}
1753

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