1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 1662 unchanged lines hidden (view full) ---

1671 priority_list = cpu.randomPriority();
1672 break;
1673 default:
1674 panic("Invalid thread policy");
1675 }
1676
1677 for (auto tid : priority_list) {
1678 ExecuteThreadInfo &ex_info = executeInfo[tid];
1679
1680 bool is_thread_active =
1681 cpu.getContext(tid)->status() == ThreadContext::Active;
1682 bool can_commit_insts = !ex_info.inFlightInsts->empty() &&
1683 is_thread_active;
1684
1685 if (can_commit_insts) {
1686 QueuedInst *head_inflight_inst = &(ex_info.inFlightInsts->front());
1687 MinorDynInstPtr inst = head_inflight_inst->inst;
1688
1689 can_commit_insts = can_commit_insts &&
1690 (!inst->inLSQ || (lsq.findResponse(inst) != NULL));
1691
1692 if (!inst->inLSQ) {

--- 49 unchanged lines hidden (view full) ---

1742 case Enums::Random:
1743 priority_list = cpu.randomPriority();
1744 break;
1745 default:
1746 panic("Invalid thread scheduling policy.");
1747 }
1748
1749 for (auto tid : priority_list) {
1750 if (cpu.getContext(tid)->status() == ThreadContext::Active &&
1751 getInput(tid)) {
1752 issuePriority = tid;
1753 return tid;
1754 }
1755 }
1756
1757 return InvalidThreadID;
1758}
1759

--- 115 unchanged lines hidden ---