exec_context.hh (14105:969b4e972b07) exec_context.hh (14297:b4519e586f5e)
1/*
2 * Copyright (c) 2011-2014, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 119 unchanged lines hidden (view full) ---

128 {
129 assert(byteEnable.empty() || byteEnable.size() == size);
130 return execute.getLSQ().pushRequest(inst, false /* store */, data,
131 size, addr, flags, res, nullptr, byteEnable);
132 }
133
134 Fault
135 initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
1/*
2 * Copyright (c) 2011-2014, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 119 unchanged lines hidden (view full) ---

128 {
129 assert(byteEnable.empty() || byteEnable.size() == size);
130 return execute.getLSQ().pushRequest(inst, false /* store */, data,
131 size, addr, flags, res, nullptr, byteEnable);
132 }
133
134 Fault
135 initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
136 AtomicOpFunctor *amo_op) override
136 AtomicOpFunctorPtr amo_op) override
137 {
138 // AMO requests are pushed through the store path
139 return execute.getLSQ().pushRequest(inst, false /* amo */, nullptr,
137 {
138 // AMO requests are pushed through the store path
139 return execute.getLSQ().pushRequest(inst, false /* amo */, nullptr,
140 size, addr, flags, nullptr, amo_op);
140 size, addr, flags, nullptr, std::move(amo_op));
141 }
142
143 RegVal
144 readIntRegOperand(const StaticInst *si, int idx) override
145 {
146 const RegId& reg = si->srcRegIdx(idx);
147 assert(reg.isIntReg());
148 return thread.readIntReg(reg.index());

--- 314 unchanged lines hidden --- 		141 }
142
143 RegVal
144 readIntRegOperand(const StaticInst *si, int idx) override
145 {
146 const RegId& reg = si->srcRegIdx(idx);
147 assert(reg.isIntReg());
148 return thread.readIntReg(reg.index());

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