exec_context.hh (13953:43ae8a30ec1f) exec_context.hh (13954:2f400a5f2627)
1/*
2 * Copyright (c) 2011-2014, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 82 unchanged lines hidden (view full) ---

91 MinorDynInstPtr inst_) :
92 cpu(cpu_),
93 thread(thread_),
94 execute(execute_),
95 inst(inst_)
96 {
97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
98 pcState(inst->pc);
1/*
2 * Copyright (c) 2011-2014, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 82 unchanged lines hidden (view full) ---

91 MinorDynInstPtr inst_) :
92 cpu(cpu_),
93 thread(thread_),
94 execute(execute_),
95 inst(inst_)
96 {
97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
98 pcState(inst->pc);
99 setPredicate(true);
99 setPredicate(inst->readPredicate());
100 setMemAccPredicate(inst->readMemAccPredicate());
100 thread.setIntReg(TheISA::ZeroReg, 0);
101#if THE_ISA == ALPHA_ISA
102 thread.setFloatReg(TheISA::ZeroReg, 0);
103#endif
104 }
105
101 thread.setIntReg(TheISA::ZeroReg, 0);
102#if THE_ISA == ALPHA_ISA
103 thread.setFloatReg(TheISA::ZeroReg, 0);
104#endif
105 }
106
107 ~ExecContext()
108 {
109 inst->setPredicate(readPredicate());
110 inst->setMemAccPredicate(readMemAccPredicate());
111 }
112
106 Fault
107 initiateMemRead(Addr addr, unsigned int size,
113 Fault
114 initiateMemRead(Addr addr, unsigned int size,
108 Request::Flags flags) override
115 Request::Flags flags,
116 const std::vector<bool>& byteEnable = std::vector<bool>())
117 override
109 {
110 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
118 {
119 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
111 size, addr, flags, NULL, nullptr);
120 size, addr, flags, nullptr, nullptr, byteEnable);
112 return NoFault;
113 }
114
115 Fault
116 writeMem(uint8_t *data, unsigned int size, Addr addr,
121 return NoFault;
122 }
123
124 Fault
125 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
126 Request::Flags flags, uint64_t *res,
127 const std::vector<bool>& byteEnable = std::vector<bool>())
128 override
118 {
129 {
130 assert(byteEnable.empty() || byteEnable.size() == size);
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
131 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res, nullptr);
132 size, addr, flags, res, nullptr, byteEnable);
121 return NoFault;
122 }
123
124 Fault
125 initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
126 AtomicOpFunctor *amo_op) override
127 {
128 // AMO requests are pushed through the store path

--- 325 unchanged lines hidden --- 		133 return NoFault;
134 }
135
136 Fault
137 initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags,
138 AtomicOpFunctor *amo_op) override
139 {
140 // AMO requests are pushed through the store path

--- 325 unchanged lines hidden ---