exec_context.hh (13598:39220222740c) exec_context.hh (13610:5d5404ac6288)
1/*
1/*
2 * Copyright (c) 2011-2014, 2016 ARM Limited
2 * Copyright (c) 2011-2014, 2016-2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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156 TheISA::VecElem
157 readVecElemOperand(const StaticInst *si, int idx) const override
158 {
159 const RegId& reg = si->srcRegIdx(idx);
160 assert(reg.isVecElem());
161 return thread.readVecElem(reg);
162 }
163
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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156 TheISA::VecElem
157 readVecElemOperand(const StaticInst *si, int idx) const override
158 {
159 const RegId& reg = si->srcRegIdx(idx);
160 assert(reg.isVecElem());
161 return thread.readVecElem(reg);
162 }
163
164 const TheISA::VecPredRegContainer&
165 readVecPredRegOperand(const StaticInst *si, int idx) const override
166 {
167 const RegId& reg = si->srcRegIdx(idx);
168 assert(reg.isVecPredReg());
169 return thread.readVecPredReg(reg);
170 }
171
172 TheISA::VecPredRegContainer&
173 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
174 {
175 const RegId& reg = si->destRegIdx(idx);
176 assert(reg.isVecPredReg());
177 return thread.getWritableVecPredReg(reg);
178 }
179
164 void
165 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
166 {
167 const RegId& reg = si->destRegIdx(idx);
168 assert(reg.isIntReg());
169 thread.setIntReg(reg.index(), val);
170 }
171

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181 setVecRegOperand(const StaticInst *si, int idx,
182 const TheISA::VecRegContainer& val) override
183 {
184 const RegId& reg = si->destRegIdx(idx);
185 assert(reg.isVecReg());
186 thread.setVecReg(reg, val);
187 }
188
180 void
181 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
182 {
183 const RegId& reg = si->destRegIdx(idx);
184 assert(reg.isIntReg());
185 thread.setIntReg(reg.index(), val);
186 }
187

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197 setVecRegOperand(const StaticInst *si, int idx,
198 const TheISA::VecRegContainer& val) override
199 {
200 const RegId& reg = si->destRegIdx(idx);
201 assert(reg.isVecReg());
202 thread.setVecReg(reg, val);
203 }
204
205 void
206 setVecPredRegOperand(const StaticInst *si, int idx,
207 const TheISA::VecPredRegContainer& val)
208 {
209 const RegId& reg = si->destRegIdx(idx);
210 assert(reg.isVecPredReg());
211 thread.setVecPredReg(reg, val);
212 }
213
189 /** Vector Register Lane Interfaces. */
190 /** @{ */
191 /** Reads source vector 8bit operand. */
192 ConstVecLane8
193 readVec8BitLaneOperand(const StaticInst *si, int idx) const
194 override
195 {
196 const RegId& reg = si->srcRegIdx(idx);

--- 275 unchanged lines hidden --- 		214 /** Vector Register Lane Interfaces. */
215 /** @{ */
216 /** Reads source vector 8bit operand. */
217 ConstVecLane8
218 readVec8BitLaneOperand(const StaticInst *si, int idx) const
219 override
220 {
221 const RegId& reg = si->srcRegIdx(idx);

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