exec_context.hh (13500:6e0a2a7c6d8c) exec_context.hh (13557:fc33e6048b25)
1/*
2 * Copyright (c) 2011-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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116 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
118 {
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
1/*
2 * Copyright (c) 2011-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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116 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
118 {
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
124 IntReg
124 RegVal
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
127 const RegId& reg = si->srcRegIdx(idx);
128 assert(reg.isIntReg());
129 return thread.readIntReg(reg.index());
130 }
131
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
127 const RegId& reg = si->srcRegIdx(idx);
128 assert(reg.isIntReg());
129 return thread.readIntReg(reg.index());
130 }
131
132 TheISA::FloatRegBits
132 RegVal
133 readFloatRegOperandBits(const StaticInst *si, int idx) override
134 {
135 const RegId& reg = si->srcRegIdx(idx);
136 assert(reg.isFloatReg());
137 return thread.readFloatRegBits(reg.index());
138 }
139
133 readFloatRegOperandBits(const StaticInst *si, int idx) override
134 {
135 const RegId& reg = si->srcRegIdx(idx);
136 assert(reg.isFloatReg());
137 return thread.readFloatRegBits(reg.index());
138 }
139
140 const TheISA::VecRegContainer&
140 const TheISA::VecRegContainer &
141 readVecRegOperand(const StaticInst *si, int idx) const override
142 {
143 const RegId& reg = si->srcRegIdx(idx);
144 assert(reg.isVecReg());
145 return thread.readVecReg(reg);
146 }
147
141 readVecRegOperand(const StaticInst *si, int idx) const override
142 {
143 const RegId& reg = si->srcRegIdx(idx);
144 assert(reg.isVecReg());
145 return thread.readVecReg(reg);
146 }
147
148 TheISA::VecRegContainer&
148 TheISA::VecRegContainer &
149 getWritableVecRegOperand(const StaticInst *si, int idx) override
150 {
151 const RegId& reg = si->destRegIdx(idx);
152 assert(reg.isVecReg());
153 return thread.getWritableVecReg(reg);
154 }
155
156 TheISA::VecElem
157 readVecElemOperand(const StaticInst *si, int idx) const override
158 {
159 const RegId& reg = si->srcRegIdx(idx);
160 assert(reg.isVecReg());
161 return thread.readVecElem(reg);
162 }
163
164 void
149 getWritableVecRegOperand(const StaticInst *si, int idx) override
150 {
151 const RegId& reg = si->destRegIdx(idx);
152 assert(reg.isVecReg());
153 return thread.getWritableVecReg(reg);
154 }
155
156 TheISA::VecElem
157 readVecElemOperand(const StaticInst *si, int idx) const override
158 {
159 const RegId& reg = si->srcRegIdx(idx);
160 assert(reg.isVecReg());
161 return thread.readVecElem(reg);
162 }
163
164 void
165 setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
165 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
166 {
167 const RegId& reg = si->destRegIdx(idx);
168 assert(reg.isIntReg());
169 thread.setIntReg(reg.index(), val);
170 }
171
172 void
166 {
167 const RegId& reg = si->destRegIdx(idx);
168 assert(reg.isIntReg());
169 thread.setIntReg(reg.index(), val);
170 }
171
172 void
173 setFloatRegOperandBits(const StaticInst *si, int idx,
174 TheISA::FloatRegBits val) override
173 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
175 {
176 const RegId& reg = si->destRegIdx(idx);
177 assert(reg.isFloatReg());
178 thread.setFloatRegBits(reg.index(), val);
179 }
180
181 void
182 setVecRegOperand(const StaticInst *si, int idx,

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227 const RegId& reg = si->srcRegIdx(idx);
228 assert(reg.isVecReg());
229 return thread.readVec64BitLaneReg(reg);
230 }
231
232 /** Write a lane of the destination vector operand. */
233 template <typename LD>
234 void
174 {
175 const RegId& reg = si->destRegIdx(idx);
176 assert(reg.isFloatReg());
177 thread.setFloatRegBits(reg.index(), val);
178 }
179
180 void
181 setVecRegOperand(const StaticInst *si, int idx,

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226 const RegId& reg = si->srcRegIdx(idx);
227 assert(reg.isVecReg());
228 return thread.readVec64BitLaneReg(reg);
229 }
230
231 /** Write a lane of the destination vector operand. */
232 template <typename LD>
233 void
235 setVecLaneOperandT(const StaticInst *si, int idx,
236 const LD& val)
234 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
237 {
238 const RegId& reg = si->destRegIdx(idx);
239 assert(reg.isVecReg());
240 return thread.setVecLane(reg, val);
241 }
242 virtual void
243 setVecLaneOperand(const StaticInst *si, int idx,
244 const LaneData<LaneSize::Byte>& val) override

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293 }
294
295 void
296 pcState(const TheISA::PCState &val) override
297 {
298 thread.pcState(val);
299 }
300
235 {
236 const RegId& reg = si->destRegIdx(idx);
237 assert(reg.isVecReg());
238 return thread.setVecLane(reg, val);
239 }
240 virtual void
241 setVecLaneOperand(const StaticInst *si, int idx,
242 const LaneData<LaneSize::Byte>& val) override

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291 }
292
293 void
294 pcState(const TheISA::PCState &val) override
295 {
296 thread.pcState(val);
297 }
298
301 TheISA::MiscReg
299 RegVal
302 readMiscRegNoEffect(int misc_reg) const
303 {
304 return thread.readMiscRegNoEffect(misc_reg);
305 }
306
300 readMiscRegNoEffect(int misc_reg) const
301 {
302 return thread.readMiscRegNoEffect(misc_reg);
303 }
304
307 TheISA::MiscReg
305 RegVal
308 readMiscReg(int misc_reg) override
309 {
310 return thread.readMiscReg(misc_reg);
311 }
312
313 void
306 readMiscReg(int misc_reg) override
307 {
308 return thread.readMiscReg(misc_reg);
309 }
310
311 void
314 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
312 setMiscReg(int misc_reg, const RegVal &val) override
315 {
316 thread.setMiscReg(misc_reg, val);
317 }
318
313 {
314 thread.setMiscReg(misc_reg, val);
315 }
316
319 TheISA::MiscReg
317 RegVal
320 readMiscRegOperand(const StaticInst *si, int idx) override
321 {
322 const RegId& reg = si->srcRegIdx(idx);
323 assert(reg.isMiscReg());
324 return thread.readMiscReg(reg.index());
325 }
326
327 void
328 setMiscRegOperand(const StaticInst *si, int idx,
318 readMiscRegOperand(const StaticInst *si, int idx) override
319 {
320 const RegId& reg = si->srcRegIdx(idx);
321 assert(reg.isMiscReg());
322 return thread.readMiscReg(reg.index());
323 }
324
325 void
326 setMiscRegOperand(const StaticInst *si, int idx,
329 const TheISA::MiscReg &val) override
327 const RegVal &val) override
330 {
331 const RegId& reg = si->destRegIdx(idx);
332 assert(reg.isMiscReg());
333 return thread.setMiscReg(reg.index(), val);
334 }
335
336 Fault
337 hwrei() override

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350 return thread.simPalCheck(palFunc);
351#else
352 return false;
353#endif
354 }
355
356 void
357 syscall(int64_t callnum, Fault *fault) override
328 {
329 const RegId& reg = si->destRegIdx(idx);
330 assert(reg.isMiscReg());
331 return thread.setMiscReg(reg.index(), val);
332 }
333
334 Fault
335 hwrei() override

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348 return thread.simPalCheck(palFunc);
349#else
350 return false;
351#endif
352 }
353
354 void
355 syscall(int64_t callnum, Fault *fault) override
358 {
356 {
359 if (FullSystem)
360 panic("Syscall emulation isn't available in FS mode.\n");
361
362 thread.syscall(callnum, fault);
363 }
364
365 ThreadContext *tcBase() override { return thread.getTC(); }
366

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405 demapDataPage(Addr vaddr, uint64_t asn)
406 {
407 thread.getDTBPtr()->demapPage(vaddr, asn);
408 }
409
410 BaseCPU *getCpuPtr() { return &cpu; }
411
412 /* MIPS: other thread register reading/writing */
357 if (FullSystem)
358 panic("Syscall emulation isn't available in FS mode.\n");
359
360 thread.syscall(callnum, fault);
361 }
362
363 ThreadContext *tcBase() override { return thread.getTC(); }
364

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403 demapDataPage(Addr vaddr, uint64_t asn)
404 {
405 thread.getDTBPtr()->demapPage(vaddr, asn);
406 }
407
408 BaseCPU *getCpuPtr() { return &cpu; }
409
410 /* MIPS: other thread register reading/writing */
413 uint64_t
414 readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
411 RegVal
412 readRegOtherThread(const RegId &reg, ThreadID tid=InvalidThreadID)
415 {
416 SimpleThread *other_thread = (tid == InvalidThreadID
417 ? &thread : cpu.threads[tid]);
418
419 switch (reg.classValue()) {
420 case IntRegClass:
421 return other_thread->readIntReg(reg.index());
422 break;

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428 default:
429 panic("Unexpected reg class! (%s)",
430 reg.className());
431 return 0;
432 }
433 }
434
435 void
413 {
414 SimpleThread *other_thread = (tid == InvalidThreadID
415 ? &thread : cpu.threads[tid]);
416
417 switch (reg.classValue()) {
418 case IntRegClass:
419 return other_thread->readIntReg(reg.index());
420 break;

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426 default:
427 panic("Unexpected reg class! (%s)",
428 reg.className());
429 return 0;
430 }
431 }
432
433 void
436 setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val,
437 ThreadID tid = InvalidThreadID)
434 setRegOtherThread(const RegId &reg, const RegVal &val,
435 ThreadID tid=InvalidThreadID)
438 {
439 SimpleThread *other_thread = (tid == InvalidThreadID
440 ? &thread : cpu.threads[tid]);
441
442 switch (reg.classValue()) {
443 case IntRegClass:
444 return other_thread->setIntReg(reg.index(), val);
445 break;

--- 29 unchanged lines hidden --- 		436 {
437 SimpleThread *other_thread = (tid == InvalidThreadID
438 ? &thread : cpu.threads[tid]);
439
440 switch (reg.classValue()) {
441 case IntRegClass:
442 return other_thread->setIntReg(reg.index(), val);
443 break;

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