exec_context.hh (12109:f29e9c5418aa) exec_context.hh (12420:f5c80f4ed41f)
1/*
2 * Copyright (c) 2011-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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419 }
420
421 void
422 demapDataPage(Addr vaddr, uint64_t asn)
423 {
424 thread.getDTBPtr()->demapPage(vaddr, asn);
425 }
426
1/*
2 * Copyright (c) 2011-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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419 }
420
421 void
422 demapDataPage(Addr vaddr, uint64_t asn)
423 {
424 thread.getDTBPtr()->demapPage(vaddr, asn);
425 }
426
427 /* ALPHA/POWER: Effective address storage */
428 void setEA(Addr ea) override
429 {
430 inst->ea = ea;
431 }
432
433 BaseCPU *getCpuPtr() { return &cpu; }
434
427 BaseCPU *getCpuPtr() { return &cpu; }
428
435 /* POWER: Effective address storage */
436 Addr getEA() const override
437 {
438 return inst->ea;
439 }
440
441 /* MIPS: other thread register reading/writing */
442 uint64_t
443 readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
444 {
445 SimpleThread *other_thread = (tid == InvalidThreadID
446 ? &thread : cpu.threads[tid]);
447
448 switch (reg.classValue()) {

--- 55 unchanged lines hidden --- 		429 /* MIPS: other thread register reading/writing */
430 uint64_t
431 readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
432 {
433 SimpleThread *other_thread = (tid == InvalidThreadID
434 ? &thread : cpu.threads[tid]);
435
436 switch (reg.classValue()) {

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