exec_context.hh (11877:5ea85692a53e) exec_context.hh (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
124 IntReg
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
124 IntReg
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
127 return thread.readIntReg(si->srcRegIdx(idx));
127 RegId reg = si->srcRegIdx(idx);
128 assert(reg.regClass == IntRegClass);
129 return thread.readIntReg(reg.regIdx);
128 }
129
130 TheISA::FloatReg
131 readFloatRegOperand(const StaticInst *si, int idx) override
132 {
130 }
131
132 TheISA::FloatReg
133 readFloatRegOperand(const StaticInst *si, int idx) override
134 {
133 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
134 return thread.readFloatReg(reg_idx);
135 RegId reg = si->srcRegIdx(idx);
136 assert(reg.regClass == FloatRegClass);
137 return thread.readFloatReg(reg.regIdx);
135 }
136
137 TheISA::FloatRegBits
138 readFloatRegOperandBits(const StaticInst *si, int idx) override
139 {
138 }
139
140 TheISA::FloatRegBits
141 readFloatRegOperandBits(const StaticInst *si, int idx) override
142 {
140 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
141 return thread.readFloatRegBits(reg_idx);
143 RegId reg = si->srcRegIdx(idx);
144 assert(reg.regClass == FloatRegClass);
145 return thread.readFloatRegBits(reg.regIdx);
142 }
143
144 void
145 setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
146 {
146 }
147
148 void
149 setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
150 {
147 thread.setIntReg(si->destRegIdx(idx), val);
151 RegId reg = si->destRegIdx(idx);
152 assert(reg.regClass == IntRegClass);
153 thread.setIntReg(reg.regIdx, val);
148 }
149
150 void
151 setFloatRegOperand(const StaticInst *si, int idx,
152 TheISA::FloatReg val) override
153 {
154 }
155
156 void
157 setFloatRegOperand(const StaticInst *si, int idx,
158 TheISA::FloatReg val) override
159 {
154 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
155 thread.setFloatReg(reg_idx, val);
160 RegId reg = si->destRegIdx(idx);
161 assert(reg.regClass == FloatRegClass);
162 thread.setFloatReg(reg.regIdx, val);
156 }
157
158 void
159 setFloatRegOperandBits(const StaticInst *si, int idx,
160 TheISA::FloatRegBits val) override
161 {
163 }
164
165 void
166 setFloatRegOperandBits(const StaticInst *si, int idx,
167 TheISA::FloatRegBits val) override
168 {
162 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
163 thread.setFloatRegBits(reg_idx, val);
169 RegId reg = si->destRegIdx(idx);
170 assert(reg.regClass == FloatRegClass);
171 thread.setFloatRegBits(reg.regIdx, val);
164 }
165
166 bool
167 readPredicate() override
168 {
169 return thread.readPredicate();
170 }
171

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203 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
204 {
205 thread.setMiscReg(misc_reg, val);
206 }
207
208 TheISA::MiscReg
209 readMiscRegOperand(const StaticInst *si, int idx) override
210 {
172 }
173
174 bool
175 readPredicate() override
176 {
177 return thread.readPredicate();
178 }
179

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211 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
212 {
213 thread.setMiscReg(misc_reg, val);
214 }
215
216 TheISA::MiscReg
217 readMiscRegOperand(const StaticInst *si, int idx) override
218 {
211 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
212 return thread.readMiscReg(reg_idx);
219 RegId reg = si->srcRegIdx(idx);
220 assert(reg.regClass == MiscRegClass);
221 return thread.readMiscReg(reg.regIdx);
213 }
214
215 void
216 setMiscRegOperand(const StaticInst *si, int idx,
217 const TheISA::MiscReg &val) override
218 {
222 }
223
224 void
225 setMiscRegOperand(const StaticInst *si, int idx,
226 const TheISA::MiscReg &val) override
227 {
219 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
220 return thread.setMiscReg(reg_idx, val);
228 RegId reg = si->destRegIdx(idx);
229 assert(reg.regClass == MiscRegClass);
230 return thread.setMiscReg(reg.regIdx, val);
221 }
222
223 Fault
224 hwrei() override
225 {
226#if THE_ISA == ALPHA_ISA
227 return thread.hwrei();
228#else

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264 {
265 thread.getITBPtr()->demapPage(vaddr, asn);
266 thread.getDTBPtr()->demapPage(vaddr, asn);
267 }
268
269 TheISA::CCReg
270 readCCRegOperand(const StaticInst *si, int idx) override
271 {
231 }
232
233 Fault
234 hwrei() override
235 {
236#if THE_ISA == ALPHA_ISA
237 return thread.hwrei();
238#else

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274 {
275 thread.getITBPtr()->demapPage(vaddr, asn);
276 thread.getDTBPtr()->demapPage(vaddr, asn);
277 }
278
279 TheISA::CCReg
280 readCCRegOperand(const StaticInst *si, int idx) override
281 {
272 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
273 return thread.readCCReg(reg_idx);
282 RegId reg = si->srcRegIdx(idx);
283 assert(reg.regClass == CCRegClass);
284 return thread.readCCReg(reg.regIdx);
274 }
275
276 void
277 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
278 {
285 }
286
287 void
288 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
289 {
279 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
280 thread.setCCReg(reg_idx, val);
290 RegId reg = si->destRegIdx(idx);
291 assert(reg.regClass == CCRegClass);
292 thread.setCCReg(reg.regIdx, val);
281 }
282
283 void
284 demapInstPage(Addr vaddr, uint64_t asn)
285 {
286 thread.getITBPtr()->demapPage(vaddr, asn);
287 }
288

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303 /* POWER: Effective address storage */
304 Addr getEA() const override
305 {
306 return inst->ea;
307 }
308
309 /* MIPS: other thread register reading/writing */
310 uint64_t
293 }
294
295 void
296 demapInstPage(Addr vaddr, uint64_t asn)
297 {
298 thread.getITBPtr()->demapPage(vaddr, asn);
299 }
300

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315 /* POWER: Effective address storage */
316 Addr getEA() const override
317 {
318 return inst->ea;
319 }
320
321 /* MIPS: other thread register reading/writing */
322 uint64_t
311 readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
323 readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID)
312 {
313 SimpleThread *other_thread = (tid == InvalidThreadID
314 ? &thread : cpu.threads[tid]);
315
324 {
325 SimpleThread *other_thread = (tid == InvalidThreadID
326 ? &thread : cpu.threads[tid]);
327
316 if (idx < TheISA::FP_Reg_Base) { /* Integer */
317 return other_thread->readIntReg(idx);
318 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
319 return other_thread->readFloatRegBits(idx
320 - TheISA::FP_Reg_Base);
321 } else { /* Misc */
322 return other_thread->readMiscReg(idx
323 - TheISA::Misc_Reg_Base);
328 switch(reg.regClass) {
329 case IntRegClass:
330 return other_thread->readIntReg(reg.regIdx);
331 break;
332 case FloatRegClass:
333 return other_thread->readFloatRegBits(reg.regIdx);
334 break;
335 case MiscRegClass:
336 return other_thread->readMiscReg(reg.regIdx);
337 default:
338 panic("Unexpected reg class! (%s)",
339 RegClassStrings[reg.regClass]);
340 return 0;
324 }
325 }
326
327 void
341 }
342 }
343
344 void
328 setRegOtherThread(int idx, const TheISA::MiscReg &val,
345 setRegOtherThread(RegId reg, const TheISA::MiscReg &val,
329 ThreadID tid = InvalidThreadID)
330 {
331 SimpleThread *other_thread = (tid == InvalidThreadID
332 ? &thread : cpu.threads[tid]);
333
346 ThreadID tid = InvalidThreadID)
347 {
348 SimpleThread *other_thread = (tid == InvalidThreadID
349 ? &thread : cpu.threads[tid]);
350
334 if (idx < TheISA::FP_Reg_Base) { /* Integer */
335 return other_thread->setIntReg(idx, val);
336 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
337 return other_thread->setFloatRegBits(idx
338 - TheISA::FP_Reg_Base, val);
339 } else { /* Misc */
340 return other_thread->setMiscReg(idx
341 - TheISA::Misc_Reg_Base, val);
351 switch(reg.regClass) {
352 case IntRegClass:
353 return other_thread->setIntReg(reg.regIdx, val);
354 break;
355 case FloatRegClass:
356 return other_thread->setFloatRegBits(reg.regIdx, val);
357 break;
358 case MiscRegClass:
359 return other_thread->setMiscReg(reg.regIdx, val);
360 default:
361 panic("Unexpected reg class! (%s)",
362 RegClassStrings[reg.regClass]);
342 }
343 }
344
345 public:
346 // monitor/mwait funtions
347 void armMonitor(Addr address) override
348 { getCpuPtr()->armMonitor(inst->id.threadId, address); }
349

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364 }
365
366 public:
367 // monitor/mwait funtions
368 void armMonitor(Addr address) override
369 { getCpuPtr()->armMonitor(inst->id.threadId, address); }
370

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