exec_context.hh (10259:ebb376f73dd2) exec_context.hh (10319:4207f9bfcceb)
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
56#include "cpu/exec_context.hh"
56#include "cpu/minor/execute.hh"
57#include "cpu/minor/pipeline.hh"
58#include "cpu/base.hh"
59#include "cpu/simple_thread.hh"
60#include "debug/MinorExecute.hh"
61
62namespace Minor
63{
64
65/* Forward declaration of Execute */
66class Execute;
67
68/** ExecContext bears the exec_context interface for Minor. This nicely
69 * separates that interface from other classes such as Pipeline, MinorCPU
70 * and DynMinorInst and makes it easier to see what state is accessed by it.
71 */
57#include "cpu/minor/execute.hh"
58#include "cpu/minor/pipeline.hh"
59#include "cpu/base.hh"
60#include "cpu/simple_thread.hh"
61#include "debug/MinorExecute.hh"
62
63namespace Minor
64{
65
66/* Forward declaration of Execute */
67class Execute;
68
69/** ExecContext bears the exec_context interface for Minor. This nicely
70 * separates that interface from other classes such as Pipeline, MinorCPU
71 * and DynMinorInst and makes it easier to see what state is accessed by it.
72 */
72class ExecContext
73class ExecContext : public ::ExecContext
73{
74 public:
75 MinorCPU &cpu;
76
77 /** ThreadState object, provides all the architectural state. */
78 SimpleThread &thread;
79
80 /** The execute stage so we can peek at its contents. */

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114 writeMem(uint8_t *data, unsigned int size, Addr addr,
115 unsigned int flags, uint64_t *res)
116 {
117 execute.getLSQ().pushRequest(inst, false /* store */, data,
118 size, addr, flags, res);
119 return NoFault;
120 }
121
74{
75 public:
76 MinorCPU &cpu;
77
78 /** ThreadState object, provides all the architectural state. */
79 SimpleThread &thread;
80
81 /** The execute stage so we can peek at its contents. */

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115 writeMem(uint8_t *data, unsigned int size, Addr addr,
116 unsigned int flags, uint64_t *res)
117 {
118 execute.getLSQ().pushRequest(inst, false /* store */, data,
119 size, addr, flags, res);
120 return NoFault;
121 }
122
122 uint64_t
123 IntReg
123 readIntRegOperand(const StaticInst *si, int idx)
124 {
125 return thread.readIntReg(si->srcRegIdx(idx));
126 }
127
128 TheISA::FloatReg
129 readFloatRegOperand(const StaticInst *si, int idx)
130 {

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135 TheISA::FloatRegBits
136 readFloatRegOperandBits(const StaticInst *si, int idx)
137 {
138 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
139 return thread.readFloatRegBits(reg_idx);
140 }
141
142 void
124 readIntRegOperand(const StaticInst *si, int idx)
125 {
126 return thread.readIntReg(si->srcRegIdx(idx));
127 }
128
129 TheISA::FloatReg
130 readFloatRegOperand(const StaticInst *si, int idx)
131 {

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136 TheISA::FloatRegBits
137 readFloatRegOperandBits(const StaticInst *si, int idx)
138 {
139 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
140 return thread.readFloatRegBits(reg_idx);
141 }
142
143 void
143 setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
144 setIntRegOperand(const StaticInst *si, int idx, IntReg val)
144 {
145 thread.setIntReg(si->destRegIdx(idx), val);
146 }
147
148 void
149 setFloatRegOperand(const StaticInst *si, int idx,
150 TheISA::FloatReg val)
151 {

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169
170 void
171 setPredicate(bool val)
172 {
173 thread.setPredicate(val);
174 }
175
176 TheISA::PCState
145 {
146 thread.setIntReg(si->destRegIdx(idx), val);
147 }
148
149 void
150 setFloatRegOperand(const StaticInst *si, int idx,
151 TheISA::FloatReg val)
152 {

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170
171 void
172 setPredicate(bool val)
173 {
174 thread.setPredicate(val);
175 }
176
177 TheISA::PCState
177 pcState()
178 pcState() const
178 {
179 return thread.pcState();
180 }
181
182 void
183 pcState(const TheISA::PCState &val)
184 {
185 thread.pcState(val);

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245 panic("Syscall emulation isn't available in FS mode.\n");
246
247 thread.syscall(callnum);
248 }
249
250 ThreadContext *tcBase() { return thread.getTC(); }
251
252 /* @todo, should make stCondFailures persistent somewhere */
179 {
180 return thread.pcState();
181 }
182
183 void
184 pcState(const TheISA::PCState &val)
185 {
186 thread.pcState(val);

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246 panic("Syscall emulation isn't available in FS mode.\n");
247
248 thread.syscall(callnum);
249 }
250
251 ThreadContext *tcBase() { return thread.getTC(); }
252
253 /* @todo, should make stCondFailures persistent somewhere */
253 unsigned int readStCondFailures() { return 0; }
254 unsigned int
255 setStCondFailures(unsigned int st_cond_failures)
256 {
257 return 0;
258 }
254 unsigned int readStCondFailures() const { return 0; }
255 void setStCondFailures(unsigned int st_cond_failures) {}
259
260 int contextId() { return thread.contextId(); }
261 /* ISA-specific (or at least currently ISA singleton) functions */
262
263 /* X86: TLB twiddling */
264 void
265 demapPage(Addr vaddr, uint64_t asn)
266 {

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290
291 void
292 demapDataPage(Addr vaddr, uint64_t asn)
293 {
294 thread.getDTBPtr()->demapPage(vaddr, asn);
295 }
296
297 /* ALPHA/POWER: Effective address storage */
256
257 int contextId() { return thread.contextId(); }
258 /* ISA-specific (or at least currently ISA singleton) functions */
259
260 /* X86: TLB twiddling */
261 void
262 demapPage(Addr vaddr, uint64_t asn)
263 {

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287
288 void
289 demapDataPage(Addr vaddr, uint64_t asn)
290 {
291 thread.getDTBPtr()->demapPage(vaddr, asn);
292 }
293
294 /* ALPHA/POWER: Effective address storage */
298 void setEA(Addr &ea)
295 void setEA(Addr ea)
299 {
300 inst->ea = ea;
301 }
302
303 BaseCPU *getCpuPtr() { return &cpu; }
304
305 /* POWER: Effective address storage */
296 {
297 inst->ea = ea;
298 }
299
300 BaseCPU *getCpuPtr() { return &cpu; }
301
302 /* POWER: Effective address storage */
306 Addr getEA()
303 Addr getEA() const
307 {
308 return inst->ea;
309 }
310
311 /* MIPS: other thread register reading/writing */
312 uint64_t
304 {
305 return inst->ea;
306 }
307
308 /* MIPS: other thread register reading/writing */
309 uint64_t
313 readRegOtherThread(unsigned idx, ThreadID tid = InvalidThreadID)
310 readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
314 {
315 SimpleThread *other_thread = (tid == InvalidThreadID
316 ? &thread : cpu.threads[tid]);
317
318 if (idx < TheISA::FP_Reg_Base) { /* Integer */
319 return other_thread->readIntReg(idx);
320 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
321 return other_thread->readFloatRegBits(idx
322 - TheISA::FP_Reg_Base);
323 } else { /* Misc */
324 return other_thread->readMiscReg(idx
325 - TheISA::Misc_Reg_Base);
326 }
327 }
328
329 void
311 {
312 SimpleThread *other_thread = (tid == InvalidThreadID
313 ? &thread : cpu.threads[tid]);
314
315 if (idx < TheISA::FP_Reg_Base) { /* Integer */
316 return other_thread->readIntReg(idx);
317 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
318 return other_thread->readFloatRegBits(idx
319 - TheISA::FP_Reg_Base);
320 } else { /* Misc */
321 return other_thread->readMiscReg(idx
322 - TheISA::Misc_Reg_Base);
323 }
324 }
325
326 void
330 setRegOtherThread(unsigned idx, const TheISA::MiscReg &val,
327 setRegOtherThread(int idx, const TheISA::MiscReg &val,
331 ThreadID tid = InvalidThreadID)
332 {
333 SimpleThread *other_thread = (tid == InvalidThreadID
334 ? &thread : cpu.threads[tid]);
335
336 if (idx < TheISA::FP_Reg_Base) { /* Integer */
337 return other_thread->setIntReg(idx, val);
338 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */

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329 {
330 SimpleThread *other_thread = (tid == InvalidThreadID
331 ? &thread : cpu.threads[tid]);
332
333 if (idx < TheISA::FP_Reg_Base) { /* Integer */
334 return other_thread->setIntReg(idx, val);
335 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */

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