1/* 2 * Copyright (c) 2011-2014 ARM Limited 3 * Copyright (c) 2013 Advanced Micro Devices, Inc. 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 110 unchanged lines hidden (view full) --- 119 execute.getLSQ().pushRequest(inst, false /* store */, data, 120 size, addr, flags, res); 121 return NoFault; 122 } 123 124 IntReg 125 readIntRegOperand(const StaticInst *si, int idx) override 126 { |
127 RegId reg = si->srcRegIdx(idx); 128 assert(reg.regClass == IntRegClass); 129 return thread.readIntReg(reg.regIdx); |
130 } 131 132 TheISA::FloatReg 133 readFloatRegOperand(const StaticInst *si, int idx) override 134 { |
135 RegId reg = si->srcRegIdx(idx); 136 assert(reg.regClass == FloatRegClass); 137 return thread.readFloatReg(reg.regIdx); |
138 } 139 140 TheISA::FloatRegBits 141 readFloatRegOperandBits(const StaticInst *si, int idx) override 142 { |
143 RegId reg = si->srcRegIdx(idx); 144 assert(reg.regClass == FloatRegClass); 145 return thread.readFloatRegBits(reg.regIdx); |
146 } 147 148 void 149 setIntRegOperand(const StaticInst *si, int idx, IntReg val) override 150 { |
151 RegId reg = si->destRegIdx(idx); 152 assert(reg.regClass == IntRegClass); 153 thread.setIntReg(reg.regIdx, val); |
154 } 155 156 void 157 setFloatRegOperand(const StaticInst *si, int idx, 158 TheISA::FloatReg val) override 159 { |
160 RegId reg = si->destRegIdx(idx); 161 assert(reg.regClass == FloatRegClass); 162 thread.setFloatReg(reg.regIdx, val); |
163 } 164 165 void 166 setFloatRegOperandBits(const StaticInst *si, int idx, 167 TheISA::FloatRegBits val) override 168 { |
169 RegId reg = si->destRegIdx(idx); 170 assert(reg.regClass == FloatRegClass); 171 thread.setFloatRegBits(reg.regIdx, val); |
172 } 173 174 bool 175 readPredicate() override 176 { 177 return thread.readPredicate(); 178 } 179 --- 31 unchanged lines hidden (view full) --- 211 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override 212 { 213 thread.setMiscReg(misc_reg, val); 214 } 215 216 TheISA::MiscReg 217 readMiscRegOperand(const StaticInst *si, int idx) override 218 { |
219 RegId reg = si->srcRegIdx(idx); 220 assert(reg.regClass == MiscRegClass); 221 return thread.readMiscReg(reg.regIdx); |
222 } 223 224 void 225 setMiscRegOperand(const StaticInst *si, int idx, 226 const TheISA::MiscReg &val) override 227 { |
228 RegId reg = si->destRegIdx(idx); 229 assert(reg.regClass == MiscRegClass); 230 return thread.setMiscReg(reg.regIdx, val); |
231 } 232 233 Fault 234 hwrei() override 235 { 236#if THE_ISA == ALPHA_ISA 237 return thread.hwrei(); 238#else --- 35 unchanged lines hidden (view full) --- 274 { 275 thread.getITBPtr()->demapPage(vaddr, asn); 276 thread.getDTBPtr()->demapPage(vaddr, asn); 277 } 278 279 TheISA::CCReg 280 readCCRegOperand(const StaticInst *si, int idx) override 281 { |
282 RegId reg = si->srcRegIdx(idx); 283 assert(reg.regClass == CCRegClass); 284 return thread.readCCReg(reg.regIdx); |
285 } 286 287 void 288 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override 289 { |
290 RegId reg = si->destRegIdx(idx); 291 assert(reg.regClass == CCRegClass); 292 thread.setCCReg(reg.regIdx, val); |
293 } 294 295 void 296 demapInstPage(Addr vaddr, uint64_t asn) 297 { 298 thread.getITBPtr()->demapPage(vaddr, asn); 299 } 300 --- 14 unchanged lines hidden (view full) --- 315 /* POWER: Effective address storage */ 316 Addr getEA() const override 317 { 318 return inst->ea; 319 } 320 321 /* MIPS: other thread register reading/writing */ 322 uint64_t |
323 readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID) |
324 { 325 SimpleThread *other_thread = (tid == InvalidThreadID 326 ? &thread : cpu.threads[tid]); 327 |
328 switch(reg.regClass) { 329 case IntRegClass: 330 return other_thread->readIntReg(reg.regIdx); 331 break; 332 case FloatRegClass: 333 return other_thread->readFloatRegBits(reg.regIdx); 334 break; 335 case MiscRegClass: 336 return other_thread->readMiscReg(reg.regIdx); 337 default: 338 panic("Unexpected reg class! (%s)", 339 RegClassStrings[reg.regClass]); 340 return 0; |
341 } 342 } 343 344 void |
345 setRegOtherThread(RegId reg, const TheISA::MiscReg &val, |
346 ThreadID tid = InvalidThreadID) 347 { 348 SimpleThread *other_thread = (tid == InvalidThreadID 349 ? &thread : cpu.threads[tid]); 350 |
351 switch(reg.regClass) { 352 case IntRegClass: 353 return other_thread->setIntReg(reg.regIdx, val); 354 break; 355 case FloatRegClass: 356 return other_thread->setFloatRegBits(reg.regIdx, val); 357 break; 358 case MiscRegClass: 359 return other_thread->setMiscReg(reg.regIdx, val); 360 default: 361 panic("Unexpected reg class! (%s)", 362 RegClassStrings[reg.regClass]); |
363 } 364 } 365 366 public: 367 // monitor/mwait funtions 368 void armMonitor(Addr address) override 369 { getCpuPtr()->armMonitor(inst->id.threadId, address); } 370 --- 13 unchanged lines hidden --- |