2c2
< * Copyright (c) 2011-2014, 2016 ARM Limited
---
> * Copyright (c) 2011-2014, 2016-2017 ARM Limited
163a164,179
> const TheISA::VecPredRegContainer&
> readVecPredRegOperand(const StaticInst *si, int idx) const override
> {
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isVecPredReg());
> return thread.readVecPredReg(reg);
> }
>
> TheISA::VecPredRegContainer&
> getWritableVecPredRegOperand(const StaticInst *si, int idx) override
> {
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isVecPredReg());
> return thread.getWritableVecPredReg(reg);
> }
>
188a205,213
> void
> setVecPredRegOperand(const StaticInst *si, int idx,
> const TheISA::VecPredRegContainer& val)
> {
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isVecPredReg());
> thread.setVecPredReg(reg, val);
> }
>