124c124
< IntReg
---
> RegVal
132c132
< TheISA::FloatRegBits
---
> RegVal
140c140
< const TheISA::VecRegContainer&
---
> const TheISA::VecRegContainer &
148c148
< TheISA::VecRegContainer&
---
> TheISA::VecRegContainer &
165c165
< setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
---
> setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
173,174c173
< setFloatRegOperandBits(const StaticInst *si, int idx,
< TheISA::FloatRegBits val) override
---
> setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
235,236c234
< setVecLaneOperandT(const StaticInst *si, int idx,
< const LD& val)
---
> setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
301c299
< TheISA::MiscReg
---
> RegVal
307c305
< TheISA::MiscReg
---
> RegVal
314c312
< setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
---
> setMiscReg(int misc_reg, const RegVal &val) override
319c317
< TheISA::MiscReg
---
> RegVal
329c327
< const TheISA::MiscReg &val) override
---
> const RegVal &val) override
358c356
< {
---
> {
413,414c411,412
< uint64_t
< readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
---
> RegVal
> readRegOtherThread(const RegId &reg, ThreadID tid=InvalidThreadID)
436,437c434,435
< setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val,
< ThreadID tid = InvalidThreadID)
---
> setRegOtherThread(const RegId &reg, const RegVal &val,
> ThreadID tid=InvalidThreadID)