127c127,129
< return thread.readIntReg(si->srcRegIdx(idx));
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == IntRegClass);
> return thread.readIntReg(reg.regIdx);
133,134c135,137
< int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
< return thread.readFloatReg(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> return thread.readFloatReg(reg.regIdx);
140,141c143,145
< int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
< return thread.readFloatRegBits(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> return thread.readFloatRegBits(reg.regIdx);
147c151,153
< thread.setIntReg(si->destRegIdx(idx), val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == IntRegClass);
> thread.setIntReg(reg.regIdx, val);
154,155c160,162
< int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
< thread.setFloatReg(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> thread.setFloatReg(reg.regIdx, val);
162,163c169,171
< int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
< thread.setFloatRegBits(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == FloatRegClass);
> thread.setFloatRegBits(reg.regIdx, val);
211,212c219,221
< int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
< return thread.readMiscReg(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == MiscRegClass);
> return thread.readMiscReg(reg.regIdx);
219,220c228,230
< int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
< return thread.setMiscReg(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == MiscRegClass);
> return thread.setMiscReg(reg.regIdx, val);
272,273c282,284
< int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
< return thread.readCCReg(reg_idx);
---
> RegId reg = si->srcRegIdx(idx);
> assert(reg.regClass == CCRegClass);
> return thread.readCCReg(reg.regIdx);
279,280c290,292
< int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
< thread.setCCReg(reg_idx, val);
---
> RegId reg = si->destRegIdx(idx);
> assert(reg.regClass == CCRegClass);
> thread.setCCReg(reg.regIdx, val);
311c323
< readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
---
> readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID)
316,323c328,340
< if (idx < TheISA::FP_Reg_Base) { /* Integer */
< return other_thread->readIntReg(idx);
< } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
< return other_thread->readFloatRegBits(idx
< - TheISA::FP_Reg_Base);
< } else { /* Misc */
< return other_thread->readMiscReg(idx
< - TheISA::Misc_Reg_Base);
---
> switch(reg.regClass) {
> case IntRegClass:
> return other_thread->readIntReg(reg.regIdx);
> break;
> case FloatRegClass:
> return other_thread->readFloatRegBits(reg.regIdx);
> break;
> case MiscRegClass:
> return other_thread->readMiscReg(reg.regIdx);
> default:
> panic("Unexpected reg class! (%s)",
> RegClassStrings[reg.regClass]);
> return 0;
328c345
< setRegOtherThread(int idx, const TheISA::MiscReg &val,
---
> setRegOtherThread(RegId reg, const TheISA::MiscReg &val,
334,341c351,362
< if (idx < TheISA::FP_Reg_Base) { /* Integer */
< return other_thread->setIntReg(idx, val);
< } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
< return other_thread->setFloatRegBits(idx
< - TheISA::FP_Reg_Base, val);
< } else { /* Misc */
< return other_thread->setMiscReg(idx
< - TheISA::Misc_Reg_Base, val);
---
> switch(reg.regClass) {
> case IntRegClass:
> return other_thread->setIntReg(reg.regIdx, val);
> break;
> case FloatRegClass:
> return other_thread->setFloatRegBits(reg.regIdx, val);
> break;
> case MiscRegClass:
> return other_thread->setMiscReg(reg.regIdx, val);
> default:
> panic("Unexpected reg class! (%s)",
> RegClassStrings[reg.regClass]);