1/*
| 1/*
|
2 * Copyright (c) 2011-2014, 2016 ARM Limited
| 2 * Copyright (c) 2011-2014, 2016-2017 ARM Limited
|
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 * Andrew Bardsley
45 */
46
47/**
48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
56#include "cpu/exec_context.hh"
57#include "cpu/minor/execute.hh"
58#include "cpu/minor/pipeline.hh"
59#include "cpu/base.hh"
60#include "cpu/simple_thread.hh"
61#include "mem/request.hh"
62#include "debug/MinorExecute.hh"
63
64namespace Minor
65{
66
67/* Forward declaration of Execute */
68class Execute;
69
70/** ExecContext bears the exec_context interface for Minor. This nicely
71 * separates that interface from other classes such as Pipeline, MinorCPU
72 * and DynMinorInst and makes it easier to see what state is accessed by it.
73 */
74class ExecContext : public ::ExecContext
75{
76 public:
77 MinorCPU &cpu;
78
79 /** ThreadState object, provides all the architectural state. */
80 SimpleThread &thread;
81
82 /** The execute stage so we can peek at its contents. */
83 Execute &execute;
84
85 /** Instruction for the benefit of memory operations and for PC */
86 MinorDynInstPtr inst;
87
88 ExecContext (
89 MinorCPU &cpu_,
90 SimpleThread &thread_, Execute &execute_,
91 MinorDynInstPtr inst_) :
92 cpu(cpu_),
93 thread(thread_),
94 execute(execute_),
95 inst(inst_)
96 {
97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
98 pcState(inst->pc);
99 setPredicate(true);
100 thread.setIntReg(TheISA::ZeroReg, 0);
101#if THE_ISA == ALPHA_ISA
102 thread.setFloatRegBits(TheISA::ZeroReg, 0);
103#endif
104 }
105
106 Fault
107 initiateMemRead(Addr addr, unsigned int size,
108 Request::Flags flags) override
109 {
110 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
111 size, addr, flags, NULL);
112 return NoFault;
113 }
114
115 Fault
116 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
118 {
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
124 RegVal
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
127 const RegId& reg = si->srcRegIdx(idx);
128 assert(reg.isIntReg());
129 return thread.readIntReg(reg.index());
130 }
131
132 RegVal
133 readFloatRegOperandBits(const StaticInst *si, int idx) override
134 {
135 const RegId& reg = si->srcRegIdx(idx);
136 assert(reg.isFloatReg());
137 return thread.readFloatRegBits(reg.index());
138 }
139
140 const TheISA::VecRegContainer &
141 readVecRegOperand(const StaticInst *si, int idx) const override
142 {
143 const RegId& reg = si->srcRegIdx(idx);
144 assert(reg.isVecReg());
145 return thread.readVecReg(reg);
146 }
147
148 TheISA::VecRegContainer &
149 getWritableVecRegOperand(const StaticInst *si, int idx) override
150 {
151 const RegId& reg = si->destRegIdx(idx);
152 assert(reg.isVecReg());
153 return thread.getWritableVecReg(reg);
154 }
155
156 TheISA::VecElem
157 readVecElemOperand(const StaticInst *si, int idx) const override
158 {
159 const RegId& reg = si->srcRegIdx(idx);
160 assert(reg.isVecElem());
161 return thread.readVecElem(reg);
162 }
163
| 3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 * Andrew Bardsley
45 */
46
47/**
48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
56#include "cpu/exec_context.hh"
57#include "cpu/minor/execute.hh"
58#include "cpu/minor/pipeline.hh"
59#include "cpu/base.hh"
60#include "cpu/simple_thread.hh"
61#include "mem/request.hh"
62#include "debug/MinorExecute.hh"
63
64namespace Minor
65{
66
67/* Forward declaration of Execute */
68class Execute;
69
70/** ExecContext bears the exec_context interface for Minor. This nicely
71 * separates that interface from other classes such as Pipeline, MinorCPU
72 * and DynMinorInst and makes it easier to see what state is accessed by it.
73 */
74class ExecContext : public ::ExecContext
75{
76 public:
77 MinorCPU &cpu;
78
79 /** ThreadState object, provides all the architectural state. */
80 SimpleThread &thread;
81
82 /** The execute stage so we can peek at its contents. */
83 Execute &execute;
84
85 /** Instruction for the benefit of memory operations and for PC */
86 MinorDynInstPtr inst;
87
88 ExecContext (
89 MinorCPU &cpu_,
90 SimpleThread &thread_, Execute &execute_,
91 MinorDynInstPtr inst_) :
92 cpu(cpu_),
93 thread(thread_),
94 execute(execute_),
95 inst(inst_)
96 {
97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
98 pcState(inst->pc);
99 setPredicate(true);
100 thread.setIntReg(TheISA::ZeroReg, 0);
101#if THE_ISA == ALPHA_ISA
102 thread.setFloatRegBits(TheISA::ZeroReg, 0);
103#endif
104 }
105
106 Fault
107 initiateMemRead(Addr addr, unsigned int size,
108 Request::Flags flags) override
109 {
110 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
111 size, addr, flags, NULL);
112 return NoFault;
113 }
114
115 Fault
116 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
118 {
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
124 RegVal
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
127 const RegId& reg = si->srcRegIdx(idx);
128 assert(reg.isIntReg());
129 return thread.readIntReg(reg.index());
130 }
131
132 RegVal
133 readFloatRegOperandBits(const StaticInst *si, int idx) override
134 {
135 const RegId& reg = si->srcRegIdx(idx);
136 assert(reg.isFloatReg());
137 return thread.readFloatRegBits(reg.index());
138 }
139
140 const TheISA::VecRegContainer &
141 readVecRegOperand(const StaticInst *si, int idx) const override
142 {
143 const RegId& reg = si->srcRegIdx(idx);
144 assert(reg.isVecReg());
145 return thread.readVecReg(reg);
146 }
147
148 TheISA::VecRegContainer &
149 getWritableVecRegOperand(const StaticInst *si, int idx) override
150 {
151 const RegId& reg = si->destRegIdx(idx);
152 assert(reg.isVecReg());
153 return thread.getWritableVecReg(reg);
154 }
155
156 TheISA::VecElem
157 readVecElemOperand(const StaticInst *si, int idx) const override
158 {
159 const RegId& reg = si->srcRegIdx(idx);
160 assert(reg.isVecElem());
161 return thread.readVecElem(reg);
162 }
163
|
| 164 const TheISA::VecPredRegContainer&
165 readVecPredRegOperand(const StaticInst *si, int idx) const override
166 {
167 const RegId& reg = si->srcRegIdx(idx);
168 assert(reg.isVecPredReg());
169 return thread.readVecPredReg(reg);
170 }
171
172 TheISA::VecPredRegContainer&
173 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
174 {
175 const RegId& reg = si->destRegIdx(idx);
176 assert(reg.isVecPredReg());
177 return thread.getWritableVecPredReg(reg);
178 }
179
|
164 void
165 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
166 {
167 const RegId& reg = si->destRegIdx(idx);
168 assert(reg.isIntReg());
169 thread.setIntReg(reg.index(), val);
170 }
171
172 void
173 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
174 {
175 const RegId& reg = si->destRegIdx(idx);
176 assert(reg.isFloatReg());
177 thread.setFloatRegBits(reg.index(), val);
178 }
179
180 void
181 setVecRegOperand(const StaticInst *si, int idx,
182 const TheISA::VecRegContainer& val) override
183 {
184 const RegId& reg = si->destRegIdx(idx);
185 assert(reg.isVecReg());
186 thread.setVecReg(reg, val);
187 }
188
| 180 void
181 setIntRegOperand(const StaticInst *si, int idx, RegVal val) override
182 {
183 const RegId& reg = si->destRegIdx(idx);
184 assert(reg.isIntReg());
185 thread.setIntReg(reg.index(), val);
186 }
187
188 void
189 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override
190 {
191 const RegId& reg = si->destRegIdx(idx);
192 assert(reg.isFloatReg());
193 thread.setFloatRegBits(reg.index(), val);
194 }
195
196 void
197 setVecRegOperand(const StaticInst *si, int idx,
198 const TheISA::VecRegContainer& val) override
199 {
200 const RegId& reg = si->destRegIdx(idx);
201 assert(reg.isVecReg());
202 thread.setVecReg(reg, val);
203 }
204
|
| 205 void
206 setVecPredRegOperand(const StaticInst *si, int idx,
207 const TheISA::VecPredRegContainer& val)
208 {
209 const RegId& reg = si->destRegIdx(idx);
210 assert(reg.isVecPredReg());
211 thread.setVecPredReg(reg, val);
212 }
213
|
189 /** Vector Register Lane Interfaces. */
190 /** @{ */
191 /** Reads source vector 8bit operand. */
192 ConstVecLane8
193 readVec8BitLaneOperand(const StaticInst *si, int idx) const
194 override
195 {
196 const RegId& reg = si->srcRegIdx(idx);
197 assert(reg.isVecReg());
198 return thread.readVec8BitLaneReg(reg);
199 }
200
201 /** Reads source vector 16bit operand. */
202 ConstVecLane16
203 readVec16BitLaneOperand(const StaticInst *si, int idx) const
204 override
205 {
206 const RegId& reg = si->srcRegIdx(idx);
207 assert(reg.isVecReg());
208 return thread.readVec16BitLaneReg(reg);
209 }
210
211 /** Reads source vector 32bit operand. */
212 ConstVecLane32
213 readVec32BitLaneOperand(const StaticInst *si, int idx) const
214 override
215 {
216 const RegId& reg = si->srcRegIdx(idx);
217 assert(reg.isVecReg());
218 return thread.readVec32BitLaneReg(reg);
219 }
220
221 /** Reads source vector 64bit operand. */
222 ConstVecLane64
223 readVec64BitLaneOperand(const StaticInst *si, int idx) const
224 override
225 {
226 const RegId& reg = si->srcRegIdx(idx);
227 assert(reg.isVecReg());
228 return thread.readVec64BitLaneReg(reg);
229 }
230
231 /** Write a lane of the destination vector operand. */
232 template <typename LD>
233 void
234 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
235 {
236 const RegId& reg = si->destRegIdx(idx);
237 assert(reg.isVecReg());
238 return thread.setVecLane(reg, val);
239 }
240 virtual void
241 setVecLaneOperand(const StaticInst *si, int idx,
242 const LaneData<LaneSize::Byte>& val) override
243 {
244 setVecLaneOperandT(si, idx, val);
245 }
246 virtual void
247 setVecLaneOperand(const StaticInst *si, int idx,
248 const LaneData<LaneSize::TwoByte>& val) override
249 {
250 setVecLaneOperandT(si, idx, val);
251 }
252 virtual void
253 setVecLaneOperand(const StaticInst *si, int idx,
254 const LaneData<LaneSize::FourByte>& val) override
255 {
256 setVecLaneOperandT(si, idx, val);
257 }
258 virtual void
259 setVecLaneOperand(const StaticInst *si, int idx,
260 const LaneData<LaneSize::EightByte>& val) override
261 {
262 setVecLaneOperandT(si, idx, val);
263 }
264 /** @} */
265
266 void
267 setVecElemOperand(const StaticInst *si, int idx,
268 const TheISA::VecElem val) override
269 {
270 const RegId& reg = si->destRegIdx(idx);
271 assert(reg.isVecElem());
272 thread.setVecElem(reg, val);
273 }
274
275 bool
276 readPredicate() const override
277 {
278 return thread.readPredicate();
279 }
280
281 void
282 setPredicate(bool val) override
283 {
284 thread.setPredicate(val);
285 }
286
287 TheISA::PCState
288 pcState() const override
289 {
290 return thread.pcState();
291 }
292
293 void
294 pcState(const TheISA::PCState &val) override
295 {
296 thread.pcState(val);
297 }
298
299 RegVal
300 readMiscRegNoEffect(int misc_reg) const
301 {
302 return thread.readMiscRegNoEffect(misc_reg);
303 }
304
305 RegVal
306 readMiscReg(int misc_reg) override
307 {
308 return thread.readMiscReg(misc_reg);
309 }
310
311 void
312 setMiscReg(int misc_reg, RegVal val) override
313 {
314 thread.setMiscReg(misc_reg, val);
315 }
316
317 RegVal
318 readMiscRegOperand(const StaticInst *si, int idx) override
319 {
320 const RegId& reg = si->srcRegIdx(idx);
321 assert(reg.isMiscReg());
322 return thread.readMiscReg(reg.index());
323 }
324
325 void
326 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
327 {
328 const RegId& reg = si->destRegIdx(idx);
329 assert(reg.isMiscReg());
330 return thread.setMiscReg(reg.index(), val);
331 }
332
333 Fault
334 hwrei() override
335 {
336#if THE_ISA == ALPHA_ISA
337 return thread.hwrei();
338#else
339 return NoFault;
340#endif
341 }
342
343 bool
344 simPalCheck(int palFunc) override
345 {
346#if THE_ISA == ALPHA_ISA
347 return thread.simPalCheck(palFunc);
348#else
349 return false;
350#endif
351 }
352
353 void
354 syscall(int64_t callnum, Fault *fault) override
355 {
356 if (FullSystem)
357 panic("Syscall emulation isn't available in FS mode.\n");
358
359 thread.syscall(callnum, fault);
360 }
361
362 ThreadContext *tcBase() override { return thread.getTC(); }
363
364 /* @todo, should make stCondFailures persistent somewhere */
365 unsigned int readStCondFailures() const override { return 0; }
366 void setStCondFailures(unsigned int st_cond_failures) override {}
367
368 ContextID contextId() { return thread.contextId(); }
369 /* ISA-specific (or at least currently ISA singleton) functions */
370
371 /* X86: TLB twiddling */
372 void
373 demapPage(Addr vaddr, uint64_t asn) override
374 {
375 thread.getITBPtr()->demapPage(vaddr, asn);
376 thread.getDTBPtr()->demapPage(vaddr, asn);
377 }
378
379 TheISA::CCReg
380 readCCRegOperand(const StaticInst *si, int idx) override
381 {
382 const RegId& reg = si->srcRegIdx(idx);
383 assert(reg.isCCReg());
384 return thread.readCCReg(reg.index());
385 }
386
387 void
388 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
389 {
390 const RegId& reg = si->destRegIdx(idx);
391 assert(reg.isCCReg());
392 thread.setCCReg(reg.index(), val);
393 }
394
395 void
396 demapInstPage(Addr vaddr, uint64_t asn)
397 {
398 thread.getITBPtr()->demapPage(vaddr, asn);
399 }
400
401 void
402 demapDataPage(Addr vaddr, uint64_t asn)
403 {
404 thread.getDTBPtr()->demapPage(vaddr, asn);
405 }
406
407 BaseCPU *getCpuPtr() { return &cpu; }
408
409 /* MIPS: other thread register reading/writing */
410 RegVal
411 readRegOtherThread(const RegId ®, ThreadID tid=InvalidThreadID)
412 {
413 SimpleThread *other_thread = (tid == InvalidThreadID
414 ? &thread : cpu.threads[tid]);
415
416 switch (reg.classValue()) {
417 case IntRegClass:
418 return other_thread->readIntReg(reg.index());
419 break;
420 case FloatRegClass:
421 return other_thread->readFloatRegBits(reg.index());
422 break;
423 case MiscRegClass:
424 return other_thread->readMiscReg(reg.index());
425 default:
426 panic("Unexpected reg class! (%s)",
427 reg.className());
428 return 0;
429 }
430 }
431
432 void
433 setRegOtherThread(const RegId ®, RegVal val,
434 ThreadID tid=InvalidThreadID)
435 {
436 SimpleThread *other_thread = (tid == InvalidThreadID
437 ? &thread : cpu.threads[tid]);
438
439 switch (reg.classValue()) {
440 case IntRegClass:
441 return other_thread->setIntReg(reg.index(), val);
442 break;
443 case FloatRegClass:
444 return other_thread->setFloatRegBits(reg.index(), val);
445 break;
446 case MiscRegClass:
447 return other_thread->setMiscReg(reg.index(), val);
448 default:
449 panic("Unexpected reg class! (%s)",
450 reg.className());
451 }
452 }
453
454 public:
455 // monitor/mwait funtions
456 void armMonitor(Addr address) override
457 { getCpuPtr()->armMonitor(inst->id.threadId, address); }
458
459 bool mwait(PacketPtr pkt) override
460 { return getCpuPtr()->mwait(inst->id.threadId, pkt); }
461
462 void mwaitAtomic(ThreadContext *tc) override
463 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }
464
465 AddressMonitor *getAddrMonitor() override
466 { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); }
467};
468
469}
470
471#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
| 214 /** Vector Register Lane Interfaces. */
215 /** @{ */
216 /** Reads source vector 8bit operand. */
217 ConstVecLane8
218 readVec8BitLaneOperand(const StaticInst *si, int idx) const
219 override
220 {
221 const RegId& reg = si->srcRegIdx(idx);
222 assert(reg.isVecReg());
223 return thread.readVec8BitLaneReg(reg);
224 }
225
226 /** Reads source vector 16bit operand. */
227 ConstVecLane16
228 readVec16BitLaneOperand(const StaticInst *si, int idx) const
229 override
230 {
231 const RegId& reg = si->srcRegIdx(idx);
232 assert(reg.isVecReg());
233 return thread.readVec16BitLaneReg(reg);
234 }
235
236 /** Reads source vector 32bit operand. */
237 ConstVecLane32
238 readVec32BitLaneOperand(const StaticInst *si, int idx) const
239 override
240 {
241 const RegId& reg = si->srcRegIdx(idx);
242 assert(reg.isVecReg());
243 return thread.readVec32BitLaneReg(reg);
244 }
245
246 /** Reads source vector 64bit operand. */
247 ConstVecLane64
248 readVec64BitLaneOperand(const StaticInst *si, int idx) const
249 override
250 {
251 const RegId& reg = si->srcRegIdx(idx);
252 assert(reg.isVecReg());
253 return thread.readVec64BitLaneReg(reg);
254 }
255
256 /** Write a lane of the destination vector operand. */
257 template <typename LD>
258 void
259 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val)
260 {
261 const RegId& reg = si->destRegIdx(idx);
262 assert(reg.isVecReg());
263 return thread.setVecLane(reg, val);
264 }
265 virtual void
266 setVecLaneOperand(const StaticInst *si, int idx,
267 const LaneData<LaneSize::Byte>& val) override
268 {
269 setVecLaneOperandT(si, idx, val);
270 }
271 virtual void
272 setVecLaneOperand(const StaticInst *si, int idx,
273 const LaneData<LaneSize::TwoByte>& val) override
274 {
275 setVecLaneOperandT(si, idx, val);
276 }
277 virtual void
278 setVecLaneOperand(const StaticInst *si, int idx,
279 const LaneData<LaneSize::FourByte>& val) override
280 {
281 setVecLaneOperandT(si, idx, val);
282 }
283 virtual void
284 setVecLaneOperand(const StaticInst *si, int idx,
285 const LaneData<LaneSize::EightByte>& val) override
286 {
287 setVecLaneOperandT(si, idx, val);
288 }
289 /** @} */
290
291 void
292 setVecElemOperand(const StaticInst *si, int idx,
293 const TheISA::VecElem val) override
294 {
295 const RegId& reg = si->destRegIdx(idx);
296 assert(reg.isVecElem());
297 thread.setVecElem(reg, val);
298 }
299
300 bool
301 readPredicate() const override
302 {
303 return thread.readPredicate();
304 }
305
306 void
307 setPredicate(bool val) override
308 {
309 thread.setPredicate(val);
310 }
311
312 TheISA::PCState
313 pcState() const override
314 {
315 return thread.pcState();
316 }
317
318 void
319 pcState(const TheISA::PCState &val) override
320 {
321 thread.pcState(val);
322 }
323
324 RegVal
325 readMiscRegNoEffect(int misc_reg) const
326 {
327 return thread.readMiscRegNoEffect(misc_reg);
328 }
329
330 RegVal
331 readMiscReg(int misc_reg) override
332 {
333 return thread.readMiscReg(misc_reg);
334 }
335
336 void
337 setMiscReg(int misc_reg, RegVal val) override
338 {
339 thread.setMiscReg(misc_reg, val);
340 }
341
342 RegVal
343 readMiscRegOperand(const StaticInst *si, int idx) override
344 {
345 const RegId& reg = si->srcRegIdx(idx);
346 assert(reg.isMiscReg());
347 return thread.readMiscReg(reg.index());
348 }
349
350 void
351 setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
352 {
353 const RegId& reg = si->destRegIdx(idx);
354 assert(reg.isMiscReg());
355 return thread.setMiscReg(reg.index(), val);
356 }
357
358 Fault
359 hwrei() override
360 {
361#if THE_ISA == ALPHA_ISA
362 return thread.hwrei();
363#else
364 return NoFault;
365#endif
366 }
367
368 bool
369 simPalCheck(int palFunc) override
370 {
371#if THE_ISA == ALPHA_ISA
372 return thread.simPalCheck(palFunc);
373#else
374 return false;
375#endif
376 }
377
378 void
379 syscall(int64_t callnum, Fault *fault) override
380 {
381 if (FullSystem)
382 panic("Syscall emulation isn't available in FS mode.\n");
383
384 thread.syscall(callnum, fault);
385 }
386
387 ThreadContext *tcBase() override { return thread.getTC(); }
388
389 /* @todo, should make stCondFailures persistent somewhere */
390 unsigned int readStCondFailures() const override { return 0; }
391 void setStCondFailures(unsigned int st_cond_failures) override {}
392
393 ContextID contextId() { return thread.contextId(); }
394 /* ISA-specific (or at least currently ISA singleton) functions */
395
396 /* X86: TLB twiddling */
397 void
398 demapPage(Addr vaddr, uint64_t asn) override
399 {
400 thread.getITBPtr()->demapPage(vaddr, asn);
401 thread.getDTBPtr()->demapPage(vaddr, asn);
402 }
403
404 TheISA::CCReg
405 readCCRegOperand(const StaticInst *si, int idx) override
406 {
407 const RegId& reg = si->srcRegIdx(idx);
408 assert(reg.isCCReg());
409 return thread.readCCReg(reg.index());
410 }
411
412 void
413 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
414 {
415 const RegId& reg = si->destRegIdx(idx);
416 assert(reg.isCCReg());
417 thread.setCCReg(reg.index(), val);
418 }
419
420 void
421 demapInstPage(Addr vaddr, uint64_t asn)
422 {
423 thread.getITBPtr()->demapPage(vaddr, asn);
424 }
425
426 void
427 demapDataPage(Addr vaddr, uint64_t asn)
428 {
429 thread.getDTBPtr()->demapPage(vaddr, asn);
430 }
431
432 BaseCPU *getCpuPtr() { return &cpu; }
433
434 /* MIPS: other thread register reading/writing */
435 RegVal
436 readRegOtherThread(const RegId ®, ThreadID tid=InvalidThreadID)
437 {
438 SimpleThread *other_thread = (tid == InvalidThreadID
439 ? &thread : cpu.threads[tid]);
440
441 switch (reg.classValue()) {
442 case IntRegClass:
443 return other_thread->readIntReg(reg.index());
444 break;
445 case FloatRegClass:
446 return other_thread->readFloatRegBits(reg.index());
447 break;
448 case MiscRegClass:
449 return other_thread->readMiscReg(reg.index());
450 default:
451 panic("Unexpected reg class! (%s)",
452 reg.className());
453 return 0;
454 }
455 }
456
457 void
458 setRegOtherThread(const RegId ®, RegVal val,
459 ThreadID tid=InvalidThreadID)
460 {
461 SimpleThread *other_thread = (tid == InvalidThreadID
462 ? &thread : cpu.threads[tid]);
463
464 switch (reg.classValue()) {
465 case IntRegClass:
466 return other_thread->setIntReg(reg.index(), val);
467 break;
468 case FloatRegClass:
469 return other_thread->setFloatRegBits(reg.index(), val);
470 break;
471 case MiscRegClass:
472 return other_thread->setMiscReg(reg.index(), val);
473 default:
474 panic("Unexpected reg class! (%s)",
475 reg.className());
476 }
477 }
478
479 public:
480 // monitor/mwait funtions
481 void armMonitor(Addr address) override
482 { getCpuPtr()->armMonitor(inst->id.threadId, address); }
483
484 bool mwait(PacketPtr pkt) override
485 { return getCpuPtr()->mwait(inst->id.threadId, pkt); }
486
487 void mwaitAtomic(ThreadContext *tc) override
488 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }
489
490 AddressMonitor *getAddrMonitor() override
491 { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); }
492};
493
494}
495
496#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
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