exec_context.hh (12109:f29e9c5418aa) exec_context.hh (12420:f5c80f4ed41f)
1/*
2 * Copyright (c) 2011-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 * Andrew Bardsley
45 */
46
47/**
48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
56#include "cpu/exec_context.hh"
57#include "cpu/minor/execute.hh"
58#include "cpu/minor/pipeline.hh"
59#include "cpu/base.hh"
60#include "cpu/simple_thread.hh"
61#include "mem/request.hh"
62#include "debug/MinorExecute.hh"
63
64namespace Minor
65{
66
67/* Forward declaration of Execute */
68class Execute;
69
70/** ExecContext bears the exec_context interface for Minor. This nicely
71 * separates that interface from other classes such as Pipeline, MinorCPU
72 * and DynMinorInst and makes it easier to see what state is accessed by it.
73 */
74class ExecContext : public ::ExecContext
75{
76 public:
77 MinorCPU &cpu;
78
79 /** ThreadState object, provides all the architectural state. */
80 SimpleThread &thread;
81
82 /** The execute stage so we can peek at its contents. */
83 Execute &execute;
84
85 /** Instruction for the benefit of memory operations and for PC */
86 MinorDynInstPtr inst;
87
88 ExecContext (
89 MinorCPU &cpu_,
90 SimpleThread &thread_, Execute &execute_,
91 MinorDynInstPtr inst_) :
92 cpu(cpu_),
93 thread(thread_),
94 execute(execute_),
95 inst(inst_)
96 {
97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
98 pcState(inst->pc);
99 setPredicate(true);
100 thread.setIntReg(TheISA::ZeroReg, 0);
101#if THE_ISA == ALPHA_ISA
102 thread.setFloatReg(TheISA::ZeroReg, 0.0);
103#endif
104 }
105
106 Fault
107 initiateMemRead(Addr addr, unsigned int size,
108 Request::Flags flags) override
109 {
110 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
111 size, addr, flags, NULL);
112 return NoFault;
113 }
114
115 Fault
116 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
118 {
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
124 IntReg
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
127 const RegId& reg = si->srcRegIdx(idx);
128 assert(reg.isIntReg());
129 return thread.readIntReg(reg.index());
130 }
131
132 TheISA::FloatReg
133 readFloatRegOperand(const StaticInst *si, int idx) override
134 {
135 const RegId& reg = si->srcRegIdx(idx);
136 assert(reg.isFloatReg());
137 return thread.readFloatReg(reg.index());
138 }
139
140 TheISA::FloatRegBits
141 readFloatRegOperandBits(const StaticInst *si, int idx) override
142 {
143 const RegId& reg = si->srcRegIdx(idx);
144 assert(reg.isFloatReg());
145 return thread.readFloatRegBits(reg.index());
146 }
147
148 const TheISA::VecRegContainer&
149 readVecRegOperand(const StaticInst *si, int idx) const override
150 {
151 const RegId& reg = si->srcRegIdx(idx);
152 assert(reg.isVecReg());
153 return thread.readVecReg(reg);
154 }
155
156 TheISA::VecRegContainer&
157 getWritableVecRegOperand(const StaticInst *si, int idx) override
158 {
159 const RegId& reg = si->destRegIdx(idx);
160 assert(reg.isVecReg());
161 return thread.getWritableVecReg(reg);
162 }
163
164 TheISA::VecElem
165 readVecElemOperand(const StaticInst *si, int idx) const override
166 {
167 const RegId& reg = si->srcRegIdx(idx);
168 assert(reg.isVecReg());
169 return thread.readVecElem(reg);
170 }
171
172 void
173 setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
174 {
175 const RegId& reg = si->destRegIdx(idx);
176 assert(reg.isIntReg());
177 thread.setIntReg(reg.index(), val);
178 }
179
180 void
181 setFloatRegOperand(const StaticInst *si, int idx,
182 TheISA::FloatReg val) override
183 {
184 const RegId& reg = si->destRegIdx(idx);
185 assert(reg.isFloatReg());
186 thread.setFloatReg(reg.index(), val);
187 }
188
189 void
190 setFloatRegOperandBits(const StaticInst *si, int idx,
191 TheISA::FloatRegBits val) override
192 {
193 const RegId& reg = si->destRegIdx(idx);
194 assert(reg.isFloatReg());
195 thread.setFloatRegBits(reg.index(), val);
196 }
197
198 void
199 setVecRegOperand(const StaticInst *si, int idx,
200 const TheISA::VecRegContainer& val) override
201 {
202 const RegId& reg = si->destRegIdx(idx);
203 assert(reg.isVecReg());
204 thread.setVecReg(reg, val);
205 }
206
207 /** Vector Register Lane Interfaces. */
208 /** @{ */
209 /** Reads source vector 8bit operand. */
210 ConstVecLane8
211 readVec8BitLaneOperand(const StaticInst *si, int idx) const
212 override
213 {
214 const RegId& reg = si->srcRegIdx(idx);
215 assert(reg.isVecReg());
216 return thread.readVec8BitLaneReg(reg);
217 }
218
219 /** Reads source vector 16bit operand. */
220 ConstVecLane16
221 readVec16BitLaneOperand(const StaticInst *si, int idx) const
222 override
223 {
224 const RegId& reg = si->srcRegIdx(idx);
225 assert(reg.isVecReg());
226 return thread.readVec16BitLaneReg(reg);
227 }
228
229 /** Reads source vector 32bit operand. */
230 ConstVecLane32
231 readVec32BitLaneOperand(const StaticInst *si, int idx) const
232 override
233 {
234 const RegId& reg = si->srcRegIdx(idx);
235 assert(reg.isVecReg());
236 return thread.readVec32BitLaneReg(reg);
237 }
238
239 /** Reads source vector 64bit operand. */
240 ConstVecLane64
241 readVec64BitLaneOperand(const StaticInst *si, int idx) const
242 override
243 {
244 const RegId& reg = si->srcRegIdx(idx);
245 assert(reg.isVecReg());
246 return thread.readVec64BitLaneReg(reg);
247 }
248
249 /** Write a lane of the destination vector operand. */
250 template <typename LD>
251 void
252 setVecLaneOperandT(const StaticInst *si, int idx,
253 const LD& val)
254 {
255 const RegId& reg = si->destRegIdx(idx);
256 assert(reg.isVecReg());
257 return thread.setVecLane(reg, val);
258 }
259 virtual void
260 setVecLaneOperand(const StaticInst *si, int idx,
261 const LaneData<LaneSize::Byte>& val) override
262 {
263 setVecLaneOperandT(si, idx, val);
264 }
265 virtual void
266 setVecLaneOperand(const StaticInst *si, int idx,
267 const LaneData<LaneSize::TwoByte>& val) override
268 {
269 setVecLaneOperandT(si, idx, val);
270 }
271 virtual void
272 setVecLaneOperand(const StaticInst *si, int idx,
273 const LaneData<LaneSize::FourByte>& val) override
274 {
275 setVecLaneOperandT(si, idx, val);
276 }
277 virtual void
278 setVecLaneOperand(const StaticInst *si, int idx,
279 const LaneData<LaneSize::EightByte>& val) override
280 {
281 setVecLaneOperandT(si, idx, val);
282 }
283 /** @} */
284
285 void
286 setVecElemOperand(const StaticInst *si, int idx,
287 const TheISA::VecElem val) override
288 {
289 const RegId& reg = si->destRegIdx(idx);
290 assert(reg.isVecReg());
291 thread.setVecElem(reg, val);
292 }
293
294 bool
295 readPredicate() override
296 {
297 return thread.readPredicate();
298 }
299
300 void
301 setPredicate(bool val) override
302 {
303 thread.setPredicate(val);
304 }
305
306 TheISA::PCState
307 pcState() const override
308 {
309 return thread.pcState();
310 }
311
312 void
313 pcState(const TheISA::PCState &val) override
314 {
315 thread.pcState(val);
316 }
317
318 TheISA::MiscReg
319 readMiscRegNoEffect(int misc_reg) const
320 {
321 return thread.readMiscRegNoEffect(misc_reg);
322 }
323
324 TheISA::MiscReg
325 readMiscReg(int misc_reg) override
326 {
327 return thread.readMiscReg(misc_reg);
328 }
329
330 void
331 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
332 {
333 thread.setMiscReg(misc_reg, val);
334 }
335
336 TheISA::MiscReg
337 readMiscRegOperand(const StaticInst *si, int idx) override
338 {
339 const RegId& reg = si->srcRegIdx(idx);
340 assert(reg.isMiscReg());
341 return thread.readMiscReg(reg.index());
342 }
343
344 void
345 setMiscRegOperand(const StaticInst *si, int idx,
346 const TheISA::MiscReg &val) override
347 {
348 const RegId& reg = si->destRegIdx(idx);
349 assert(reg.isMiscReg());
350 return thread.setMiscReg(reg.index(), val);
351 }
352
353 Fault
354 hwrei() override
355 {
356#if THE_ISA == ALPHA_ISA
357 return thread.hwrei();
358#else
359 return NoFault;
360#endif
361 }
362
363 bool
364 simPalCheck(int palFunc) override
365 {
366#if THE_ISA == ALPHA_ISA
367 return thread.simPalCheck(palFunc);
368#else
369 return false;
370#endif
371 }
372
373 void
374 syscall(int64_t callnum, Fault *fault) override
375 {
376 if (FullSystem)
377 panic("Syscall emulation isn't available in FS mode.\n");
378
379 thread.syscall(callnum, fault);
380 }
381
382 ThreadContext *tcBase() override { return thread.getTC(); }
383
384 /* @todo, should make stCondFailures persistent somewhere */
385 unsigned int readStCondFailures() const override { return 0; }
386 void setStCondFailures(unsigned int st_cond_failures) override {}
387
388 ContextID contextId() { return thread.contextId(); }
389 /* ISA-specific (or at least currently ISA singleton) functions */
390
391 /* X86: TLB twiddling */
392 void
393 demapPage(Addr vaddr, uint64_t asn) override
394 {
395 thread.getITBPtr()->demapPage(vaddr, asn);
396 thread.getDTBPtr()->demapPage(vaddr, asn);
397 }
398
399 TheISA::CCReg
400 readCCRegOperand(const StaticInst *si, int idx) override
401 {
402 const RegId& reg = si->srcRegIdx(idx);
403 assert(reg.isCCReg());
404 return thread.readCCReg(reg.index());
405 }
406
407 void
408 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
409 {
410 const RegId& reg = si->destRegIdx(idx);
411 assert(reg.isCCReg());
412 thread.setCCReg(reg.index(), val);
413 }
414
415 void
416 demapInstPage(Addr vaddr, uint64_t asn)
417 {
418 thread.getITBPtr()->demapPage(vaddr, asn);
419 }
420
421 void
422 demapDataPage(Addr vaddr, uint64_t asn)
423 {
424 thread.getDTBPtr()->demapPage(vaddr, asn);
425 }
426
1/*
2 * Copyright (c) 2011-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 * Andrew Bardsley
45 */
46
47/**
48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
56#include "cpu/exec_context.hh"
57#include "cpu/minor/execute.hh"
58#include "cpu/minor/pipeline.hh"
59#include "cpu/base.hh"
60#include "cpu/simple_thread.hh"
61#include "mem/request.hh"
62#include "debug/MinorExecute.hh"
63
64namespace Minor
65{
66
67/* Forward declaration of Execute */
68class Execute;
69
70/** ExecContext bears the exec_context interface for Minor. This nicely
71 * separates that interface from other classes such as Pipeline, MinorCPU
72 * and DynMinorInst and makes it easier to see what state is accessed by it.
73 */
74class ExecContext : public ::ExecContext
75{
76 public:
77 MinorCPU &cpu;
78
79 /** ThreadState object, provides all the architectural state. */
80 SimpleThread &thread;
81
82 /** The execute stage so we can peek at its contents. */
83 Execute &execute;
84
85 /** Instruction for the benefit of memory operations and for PC */
86 MinorDynInstPtr inst;
87
88 ExecContext (
89 MinorCPU &cpu_,
90 SimpleThread &thread_, Execute &execute_,
91 MinorDynInstPtr inst_) :
92 cpu(cpu_),
93 thread(thread_),
94 execute(execute_),
95 inst(inst_)
96 {
97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
98 pcState(inst->pc);
99 setPredicate(true);
100 thread.setIntReg(TheISA::ZeroReg, 0);
101#if THE_ISA == ALPHA_ISA
102 thread.setFloatReg(TheISA::ZeroReg, 0.0);
103#endif
104 }
105
106 Fault
107 initiateMemRead(Addr addr, unsigned int size,
108 Request::Flags flags) override
109 {
110 execute.getLSQ().pushRequest(inst, true /* load */, nullptr,
111 size, addr, flags, NULL);
112 return NoFault;
113 }
114
115 Fault
116 writeMem(uint8_t *data, unsigned int size, Addr addr,
117 Request::Flags flags, uint64_t *res) override
118 {
119 execute.getLSQ().pushRequest(inst, false /* store */, data,
120 size, addr, flags, res);
121 return NoFault;
122 }
123
124 IntReg
125 readIntRegOperand(const StaticInst *si, int idx) override
126 {
127 const RegId& reg = si->srcRegIdx(idx);
128 assert(reg.isIntReg());
129 return thread.readIntReg(reg.index());
130 }
131
132 TheISA::FloatReg
133 readFloatRegOperand(const StaticInst *si, int idx) override
134 {
135 const RegId& reg = si->srcRegIdx(idx);
136 assert(reg.isFloatReg());
137 return thread.readFloatReg(reg.index());
138 }
139
140 TheISA::FloatRegBits
141 readFloatRegOperandBits(const StaticInst *si, int idx) override
142 {
143 const RegId& reg = si->srcRegIdx(idx);
144 assert(reg.isFloatReg());
145 return thread.readFloatRegBits(reg.index());
146 }
147
148 const TheISA::VecRegContainer&
149 readVecRegOperand(const StaticInst *si, int idx) const override
150 {
151 const RegId& reg = si->srcRegIdx(idx);
152 assert(reg.isVecReg());
153 return thread.readVecReg(reg);
154 }
155
156 TheISA::VecRegContainer&
157 getWritableVecRegOperand(const StaticInst *si, int idx) override
158 {
159 const RegId& reg = si->destRegIdx(idx);
160 assert(reg.isVecReg());
161 return thread.getWritableVecReg(reg);
162 }
163
164 TheISA::VecElem
165 readVecElemOperand(const StaticInst *si, int idx) const override
166 {
167 const RegId& reg = si->srcRegIdx(idx);
168 assert(reg.isVecReg());
169 return thread.readVecElem(reg);
170 }
171
172 void
173 setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
174 {
175 const RegId& reg = si->destRegIdx(idx);
176 assert(reg.isIntReg());
177 thread.setIntReg(reg.index(), val);
178 }
179
180 void
181 setFloatRegOperand(const StaticInst *si, int idx,
182 TheISA::FloatReg val) override
183 {
184 const RegId& reg = si->destRegIdx(idx);
185 assert(reg.isFloatReg());
186 thread.setFloatReg(reg.index(), val);
187 }
188
189 void
190 setFloatRegOperandBits(const StaticInst *si, int idx,
191 TheISA::FloatRegBits val) override
192 {
193 const RegId& reg = si->destRegIdx(idx);
194 assert(reg.isFloatReg());
195 thread.setFloatRegBits(reg.index(), val);
196 }
197
198 void
199 setVecRegOperand(const StaticInst *si, int idx,
200 const TheISA::VecRegContainer& val) override
201 {
202 const RegId& reg = si->destRegIdx(idx);
203 assert(reg.isVecReg());
204 thread.setVecReg(reg, val);
205 }
206
207 /** Vector Register Lane Interfaces. */
208 /** @{ */
209 /** Reads source vector 8bit operand. */
210 ConstVecLane8
211 readVec8BitLaneOperand(const StaticInst *si, int idx) const
212 override
213 {
214 const RegId& reg = si->srcRegIdx(idx);
215 assert(reg.isVecReg());
216 return thread.readVec8BitLaneReg(reg);
217 }
218
219 /** Reads source vector 16bit operand. */
220 ConstVecLane16
221 readVec16BitLaneOperand(const StaticInst *si, int idx) const
222 override
223 {
224 const RegId& reg = si->srcRegIdx(idx);
225 assert(reg.isVecReg());
226 return thread.readVec16BitLaneReg(reg);
227 }
228
229 /** Reads source vector 32bit operand. */
230 ConstVecLane32
231 readVec32BitLaneOperand(const StaticInst *si, int idx) const
232 override
233 {
234 const RegId& reg = si->srcRegIdx(idx);
235 assert(reg.isVecReg());
236 return thread.readVec32BitLaneReg(reg);
237 }
238
239 /** Reads source vector 64bit operand. */
240 ConstVecLane64
241 readVec64BitLaneOperand(const StaticInst *si, int idx) const
242 override
243 {
244 const RegId& reg = si->srcRegIdx(idx);
245 assert(reg.isVecReg());
246 return thread.readVec64BitLaneReg(reg);
247 }
248
249 /** Write a lane of the destination vector operand. */
250 template <typename LD>
251 void
252 setVecLaneOperandT(const StaticInst *si, int idx,
253 const LD& val)
254 {
255 const RegId& reg = si->destRegIdx(idx);
256 assert(reg.isVecReg());
257 return thread.setVecLane(reg, val);
258 }
259 virtual void
260 setVecLaneOperand(const StaticInst *si, int idx,
261 const LaneData<LaneSize::Byte>& val) override
262 {
263 setVecLaneOperandT(si, idx, val);
264 }
265 virtual void
266 setVecLaneOperand(const StaticInst *si, int idx,
267 const LaneData<LaneSize::TwoByte>& val) override
268 {
269 setVecLaneOperandT(si, idx, val);
270 }
271 virtual void
272 setVecLaneOperand(const StaticInst *si, int idx,
273 const LaneData<LaneSize::FourByte>& val) override
274 {
275 setVecLaneOperandT(si, idx, val);
276 }
277 virtual void
278 setVecLaneOperand(const StaticInst *si, int idx,
279 const LaneData<LaneSize::EightByte>& val) override
280 {
281 setVecLaneOperandT(si, idx, val);
282 }
283 /** @} */
284
285 void
286 setVecElemOperand(const StaticInst *si, int idx,
287 const TheISA::VecElem val) override
288 {
289 const RegId& reg = si->destRegIdx(idx);
290 assert(reg.isVecReg());
291 thread.setVecElem(reg, val);
292 }
293
294 bool
295 readPredicate() override
296 {
297 return thread.readPredicate();
298 }
299
300 void
301 setPredicate(bool val) override
302 {
303 thread.setPredicate(val);
304 }
305
306 TheISA::PCState
307 pcState() const override
308 {
309 return thread.pcState();
310 }
311
312 void
313 pcState(const TheISA::PCState &val) override
314 {
315 thread.pcState(val);
316 }
317
318 TheISA::MiscReg
319 readMiscRegNoEffect(int misc_reg) const
320 {
321 return thread.readMiscRegNoEffect(misc_reg);
322 }
323
324 TheISA::MiscReg
325 readMiscReg(int misc_reg) override
326 {
327 return thread.readMiscReg(misc_reg);
328 }
329
330 void
331 setMiscReg(int misc_reg, const TheISA::MiscReg &val) override
332 {
333 thread.setMiscReg(misc_reg, val);
334 }
335
336 TheISA::MiscReg
337 readMiscRegOperand(const StaticInst *si, int idx) override
338 {
339 const RegId& reg = si->srcRegIdx(idx);
340 assert(reg.isMiscReg());
341 return thread.readMiscReg(reg.index());
342 }
343
344 void
345 setMiscRegOperand(const StaticInst *si, int idx,
346 const TheISA::MiscReg &val) override
347 {
348 const RegId& reg = si->destRegIdx(idx);
349 assert(reg.isMiscReg());
350 return thread.setMiscReg(reg.index(), val);
351 }
352
353 Fault
354 hwrei() override
355 {
356#if THE_ISA == ALPHA_ISA
357 return thread.hwrei();
358#else
359 return NoFault;
360#endif
361 }
362
363 bool
364 simPalCheck(int palFunc) override
365 {
366#if THE_ISA == ALPHA_ISA
367 return thread.simPalCheck(palFunc);
368#else
369 return false;
370#endif
371 }
372
373 void
374 syscall(int64_t callnum, Fault *fault) override
375 {
376 if (FullSystem)
377 panic("Syscall emulation isn't available in FS mode.\n");
378
379 thread.syscall(callnum, fault);
380 }
381
382 ThreadContext *tcBase() override { return thread.getTC(); }
383
384 /* @todo, should make stCondFailures persistent somewhere */
385 unsigned int readStCondFailures() const override { return 0; }
386 void setStCondFailures(unsigned int st_cond_failures) override {}
387
388 ContextID contextId() { return thread.contextId(); }
389 /* ISA-specific (or at least currently ISA singleton) functions */
390
391 /* X86: TLB twiddling */
392 void
393 demapPage(Addr vaddr, uint64_t asn) override
394 {
395 thread.getITBPtr()->demapPage(vaddr, asn);
396 thread.getDTBPtr()->demapPage(vaddr, asn);
397 }
398
399 TheISA::CCReg
400 readCCRegOperand(const StaticInst *si, int idx) override
401 {
402 const RegId& reg = si->srcRegIdx(idx);
403 assert(reg.isCCReg());
404 return thread.readCCReg(reg.index());
405 }
406
407 void
408 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val) override
409 {
410 const RegId& reg = si->destRegIdx(idx);
411 assert(reg.isCCReg());
412 thread.setCCReg(reg.index(), val);
413 }
414
415 void
416 demapInstPage(Addr vaddr, uint64_t asn)
417 {
418 thread.getITBPtr()->demapPage(vaddr, asn);
419 }
420
421 void
422 demapDataPage(Addr vaddr, uint64_t asn)
423 {
424 thread.getDTBPtr()->demapPage(vaddr, asn);
425 }
426
427 /* ALPHA/POWER: Effective address storage */
428 void setEA(Addr ea) override
429 {
430 inst->ea = ea;
431 }
432
433 BaseCPU *getCpuPtr() { return &cpu; }
434
427 BaseCPU *getCpuPtr() { return &cpu; }
428
435 /* POWER: Effective address storage */
436 Addr getEA() const override
437 {
438 return inst->ea;
439 }
440
441 /* MIPS: other thread register reading/writing */
442 uint64_t
443 readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
444 {
445 SimpleThread *other_thread = (tid == InvalidThreadID
446 ? &thread : cpu.threads[tid]);
447
448 switch (reg.classValue()) {
449 case IntRegClass:
450 return other_thread->readIntReg(reg.index());
451 break;
452 case FloatRegClass:
453 return other_thread->readFloatRegBits(reg.index());
454 break;
455 case MiscRegClass:
456 return other_thread->readMiscReg(reg.index());
457 default:
458 panic("Unexpected reg class! (%s)",
459 reg.className());
460 return 0;
461 }
462 }
463
464 void
465 setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val,
466 ThreadID tid = InvalidThreadID)
467 {
468 SimpleThread *other_thread = (tid == InvalidThreadID
469 ? &thread : cpu.threads[tid]);
470
471 switch (reg.classValue()) {
472 case IntRegClass:
473 return other_thread->setIntReg(reg.index(), val);
474 break;
475 case FloatRegClass:
476 return other_thread->setFloatRegBits(reg.index(), val);
477 break;
478 case MiscRegClass:
479 return other_thread->setMiscReg(reg.index(), val);
480 default:
481 panic("Unexpected reg class! (%s)",
482 reg.className());
483 }
484 }
485
486 public:
487 // monitor/mwait funtions
488 void armMonitor(Addr address) override
489 { getCpuPtr()->armMonitor(inst->id.threadId, address); }
490
491 bool mwait(PacketPtr pkt) override
492 { return getCpuPtr()->mwait(inst->id.threadId, pkt); }
493
494 void mwaitAtomic(ThreadContext *tc) override
495 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }
496
497 AddressMonitor *getAddrMonitor() override
498 { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); }
499};
500
501}
502
503#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
429 /* MIPS: other thread register reading/writing */
430 uint64_t
431 readRegOtherThread(const RegId& reg, ThreadID tid = InvalidThreadID)
432 {
433 SimpleThread *other_thread = (tid == InvalidThreadID
434 ? &thread : cpu.threads[tid]);
435
436 switch (reg.classValue()) {
437 case IntRegClass:
438 return other_thread->readIntReg(reg.index());
439 break;
440 case FloatRegClass:
441 return other_thread->readFloatRegBits(reg.index());
442 break;
443 case MiscRegClass:
444 return other_thread->readMiscReg(reg.index());
445 default:
446 panic("Unexpected reg class! (%s)",
447 reg.className());
448 return 0;
449 }
450 }
451
452 void
453 setRegOtherThread(const RegId& reg, const TheISA::MiscReg &val,
454 ThreadID tid = InvalidThreadID)
455 {
456 SimpleThread *other_thread = (tid == InvalidThreadID
457 ? &thread : cpu.threads[tid]);
458
459 switch (reg.classValue()) {
460 case IntRegClass:
461 return other_thread->setIntReg(reg.index(), val);
462 break;
463 case FloatRegClass:
464 return other_thread->setFloatRegBits(reg.index(), val);
465 break;
466 case MiscRegClass:
467 return other_thread->setMiscReg(reg.index(), val);
468 default:
469 panic("Unexpected reg class! (%s)",
470 reg.className());
471 }
472 }
473
474 public:
475 // monitor/mwait funtions
476 void armMonitor(Addr address) override
477 { getCpuPtr()->armMonitor(inst->id.threadId, address); }
478
479 bool mwait(PacketPtr pkt) override
480 { return getCpuPtr()->mwait(inst->id.threadId, pkt); }
481
482 void mwaitAtomic(ThreadContext *tc) override
483 { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }
484
485 AddressMonitor *getAddrMonitor() override
486 { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); }
487};
488
489}
490
491#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */