1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 * Andrew Bardsley
45 */
46
47/**
48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
| 1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Dave Greene
43 * Nathan Binkert
44 * Andrew Bardsley
45 */
46
47/**
48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
|
| 56#include "cpu/exec_context.hh"
|
56#include "cpu/minor/execute.hh"
57#include "cpu/minor/pipeline.hh"
58#include "cpu/base.hh"
59#include "cpu/simple_thread.hh"
60#include "debug/MinorExecute.hh"
61
62namespace Minor
63{
64
65/* Forward declaration of Execute */
66class Execute;
67
68/** ExecContext bears the exec_context interface for Minor. This nicely
69 * separates that interface from other classes such as Pipeline, MinorCPU
70 * and DynMinorInst and makes it easier to see what state is accessed by it.
71 */
| 57#include "cpu/minor/execute.hh"
58#include "cpu/minor/pipeline.hh"
59#include "cpu/base.hh"
60#include "cpu/simple_thread.hh"
61#include "debug/MinorExecute.hh"
62
63namespace Minor
64{
65
66/* Forward declaration of Execute */
67class Execute;
68
69/** ExecContext bears the exec_context interface for Minor. This nicely
70 * separates that interface from other classes such as Pipeline, MinorCPU
71 * and DynMinorInst and makes it easier to see what state is accessed by it.
72 */
|
72class ExecContext
| 73class ExecContext : public ::ExecContext
|
73{
74 public:
75 MinorCPU &cpu;
76
77 /** ThreadState object, provides all the architectural state. */
78 SimpleThread &thread;
79
80 /** The execute stage so we can peek at its contents. */
81 Execute &execute;
82
83 /** Instruction for the benefit of memory operations and for PC */
84 MinorDynInstPtr inst;
85
86 ExecContext (
87 MinorCPU &cpu_,
88 SimpleThread &thread_, Execute &execute_,
89 MinorDynInstPtr inst_) :
90 cpu(cpu_),
91 thread(thread_),
92 execute(execute_),
93 inst(inst_)
94 {
95 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
96 pcState(inst->pc);
97 setPredicate(true);
98 thread.setIntReg(TheISA::ZeroReg, 0);
99#if THE_ISA == ALPHA_ISA
100 thread.setFloatReg(TheISA::ZeroReg, 0.0);
101#endif
102 }
103
104 Fault
105 readMem(Addr addr, uint8_t *data, unsigned int size,
106 unsigned int flags)
107 {
108 execute.getLSQ().pushRequest(inst, true /* load */, data,
109 size, addr, flags, NULL);
110 return NoFault;
111 }
112
113 Fault
114 writeMem(uint8_t *data, unsigned int size, Addr addr,
115 unsigned int flags, uint64_t *res)
116 {
117 execute.getLSQ().pushRequest(inst, false /* store */, data,
118 size, addr, flags, res);
119 return NoFault;
120 }
121
| 74{
75 public:
76 MinorCPU &cpu;
77
78 /** ThreadState object, provides all the architectural state. */
79 SimpleThread &thread;
80
81 /** The execute stage so we can peek at its contents. */
82 Execute &execute;
83
84 /** Instruction for the benefit of memory operations and for PC */
85 MinorDynInstPtr inst;
86
87 ExecContext (
88 MinorCPU &cpu_,
89 SimpleThread &thread_, Execute &execute_,
90 MinorDynInstPtr inst_) :
91 cpu(cpu_),
92 thread(thread_),
93 execute(execute_),
94 inst(inst_)
95 {
96 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc);
97 pcState(inst->pc);
98 setPredicate(true);
99 thread.setIntReg(TheISA::ZeroReg, 0);
100#if THE_ISA == ALPHA_ISA
101 thread.setFloatReg(TheISA::ZeroReg, 0.0);
102#endif
103 }
104
105 Fault
106 readMem(Addr addr, uint8_t *data, unsigned int size,
107 unsigned int flags)
108 {
109 execute.getLSQ().pushRequest(inst, true /* load */, data,
110 size, addr, flags, NULL);
111 return NoFault;
112 }
113
114 Fault
115 writeMem(uint8_t *data, unsigned int size, Addr addr,
116 unsigned int flags, uint64_t *res)
117 {
118 execute.getLSQ().pushRequest(inst, false /* store */, data,
119 size, addr, flags, res);
120 return NoFault;
121 }
122
|
122 uint64_t
| 123 IntReg
|
123 readIntRegOperand(const StaticInst *si, int idx)
124 {
125 return thread.readIntReg(si->srcRegIdx(idx));
126 }
127
128 TheISA::FloatReg
129 readFloatRegOperand(const StaticInst *si, int idx)
130 {
131 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
132 return thread.readFloatReg(reg_idx);
133 }
134
135 TheISA::FloatRegBits
136 readFloatRegOperandBits(const StaticInst *si, int idx)
137 {
138 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
139 return thread.readFloatRegBits(reg_idx);
140 }
141
142 void
| 124 readIntRegOperand(const StaticInst *si, int idx)
125 {
126 return thread.readIntReg(si->srcRegIdx(idx));
127 }
128
129 TheISA::FloatReg
130 readFloatRegOperand(const StaticInst *si, int idx)
131 {
132 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
133 return thread.readFloatReg(reg_idx);
134 }
135
136 TheISA::FloatRegBits
137 readFloatRegOperandBits(const StaticInst *si, int idx)
138 {
139 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
140 return thread.readFloatRegBits(reg_idx);
141 }
142
143 void
|
143 setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
| 144 setIntRegOperand(const StaticInst *si, int idx, IntReg val)
|
144 {
145 thread.setIntReg(si->destRegIdx(idx), val);
146 }
147
148 void
149 setFloatRegOperand(const StaticInst *si, int idx,
150 TheISA::FloatReg val)
151 {
152 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
153 thread.setFloatReg(reg_idx, val);
154 }
155
156 void
157 setFloatRegOperandBits(const StaticInst *si, int idx,
158 TheISA::FloatRegBits val)
159 {
160 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
161 thread.setFloatRegBits(reg_idx, val);
162 }
163
164 bool
165 readPredicate()
166 {
167 return thread.readPredicate();
168 }
169
170 void
171 setPredicate(bool val)
172 {
173 thread.setPredicate(val);
174 }
175
176 TheISA::PCState
| 145 {
146 thread.setIntReg(si->destRegIdx(idx), val);
147 }
148
149 void
150 setFloatRegOperand(const StaticInst *si, int idx,
151 TheISA::FloatReg val)
152 {
153 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
154 thread.setFloatReg(reg_idx, val);
155 }
156
157 void
158 setFloatRegOperandBits(const StaticInst *si, int idx,
159 TheISA::FloatRegBits val)
160 {
161 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
162 thread.setFloatRegBits(reg_idx, val);
163 }
164
165 bool
166 readPredicate()
167 {
168 return thread.readPredicate();
169 }
170
171 void
172 setPredicate(bool val)
173 {
174 thread.setPredicate(val);
175 }
176
177 TheISA::PCState
|
177 pcState()
| 178 pcState() const
|
178 {
179 return thread.pcState();
180 }
181
182 void
183 pcState(const TheISA::PCState &val)
184 {
185 thread.pcState(val);
186 }
187
188 TheISA::MiscReg
189 readMiscRegNoEffect(int misc_reg)
190 {
191 return thread.readMiscRegNoEffect(misc_reg);
192 }
193
194 TheISA::MiscReg
195 readMiscReg(int misc_reg)
196 {
197 return thread.readMiscReg(misc_reg);
198 }
199
200 void
201 setMiscReg(int misc_reg, const TheISA::MiscReg &val)
202 {
203 thread.setMiscReg(misc_reg, val);
204 }
205
206 TheISA::MiscReg
207 readMiscRegOperand(const StaticInst *si, int idx)
208 {
209 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
210 return thread.readMiscReg(reg_idx);
211 }
212
213 void
214 setMiscRegOperand(const StaticInst *si, int idx,
215 const TheISA::MiscReg &val)
216 {
217 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
218 return thread.setMiscReg(reg_idx, val);
219 }
220
221 Fault
222 hwrei()
223 {
224#if THE_ISA == ALPHA_ISA
225 return thread.hwrei();
226#else
227 return NoFault;
228#endif
229 }
230
231 bool
232 simPalCheck(int palFunc)
233 {
234#if THE_ISA == ALPHA_ISA
235 return thread.simPalCheck(palFunc);
236#else
237 return false;
238#endif
239 }
240
241 void
242 syscall(int64_t callnum)
243 {
244 if (FullSystem)
245 panic("Syscall emulation isn't available in FS mode.\n");
246
247 thread.syscall(callnum);
248 }
249
250 ThreadContext *tcBase() { return thread.getTC(); }
251
252 /* @todo, should make stCondFailures persistent somewhere */
| 179 {
180 return thread.pcState();
181 }
182
183 void
184 pcState(const TheISA::PCState &val)
185 {
186 thread.pcState(val);
187 }
188
189 TheISA::MiscReg
190 readMiscRegNoEffect(int misc_reg)
191 {
192 return thread.readMiscRegNoEffect(misc_reg);
193 }
194
195 TheISA::MiscReg
196 readMiscReg(int misc_reg)
197 {
198 return thread.readMiscReg(misc_reg);
199 }
200
201 void
202 setMiscReg(int misc_reg, const TheISA::MiscReg &val)
203 {
204 thread.setMiscReg(misc_reg, val);
205 }
206
207 TheISA::MiscReg
208 readMiscRegOperand(const StaticInst *si, int idx)
209 {
210 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
211 return thread.readMiscReg(reg_idx);
212 }
213
214 void
215 setMiscRegOperand(const StaticInst *si, int idx,
216 const TheISA::MiscReg &val)
217 {
218 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
219 return thread.setMiscReg(reg_idx, val);
220 }
221
222 Fault
223 hwrei()
224 {
225#if THE_ISA == ALPHA_ISA
226 return thread.hwrei();
227#else
228 return NoFault;
229#endif
230 }
231
232 bool
233 simPalCheck(int palFunc)
234 {
235#if THE_ISA == ALPHA_ISA
236 return thread.simPalCheck(palFunc);
237#else
238 return false;
239#endif
240 }
241
242 void
243 syscall(int64_t callnum)
244 {
245 if (FullSystem)
246 panic("Syscall emulation isn't available in FS mode.\n");
247
248 thread.syscall(callnum);
249 }
250
251 ThreadContext *tcBase() { return thread.getTC(); }
252
253 /* @todo, should make stCondFailures persistent somewhere */
|
253 unsigned int readStCondFailures() { return 0; }
254 unsigned int
255 setStCondFailures(unsigned int st_cond_failures)
256 {
257 return 0;
258 }
| 254 unsigned int readStCondFailures() const { return 0; }
255 void setStCondFailures(unsigned int st_cond_failures) {}
|
259
260 int contextId() { return thread.contextId(); }
261 /* ISA-specific (or at least currently ISA singleton) functions */
262
263 /* X86: TLB twiddling */
264 void
265 demapPage(Addr vaddr, uint64_t asn)
266 {
267 thread.getITBPtr()->demapPage(vaddr, asn);
268 thread.getDTBPtr()->demapPage(vaddr, asn);
269 }
270
271 TheISA::CCReg
272 readCCRegOperand(const StaticInst *si, int idx)
273 {
274 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
275 return thread.readCCReg(reg_idx);
276 }
277
278 void
279 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
280 {
281 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
282 thread.setCCReg(reg_idx, val);
283 }
284
285 void
286 demapInstPage(Addr vaddr, uint64_t asn)
287 {
288 thread.getITBPtr()->demapPage(vaddr, asn);
289 }
290
291 void
292 demapDataPage(Addr vaddr, uint64_t asn)
293 {
294 thread.getDTBPtr()->demapPage(vaddr, asn);
295 }
296
297 /* ALPHA/POWER: Effective address storage */
| 256
257 int contextId() { return thread.contextId(); }
258 /* ISA-specific (or at least currently ISA singleton) functions */
259
260 /* X86: TLB twiddling */
261 void
262 demapPage(Addr vaddr, uint64_t asn)
263 {
264 thread.getITBPtr()->demapPage(vaddr, asn);
265 thread.getDTBPtr()->demapPage(vaddr, asn);
266 }
267
268 TheISA::CCReg
269 readCCRegOperand(const StaticInst *si, int idx)
270 {
271 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
272 return thread.readCCReg(reg_idx);
273 }
274
275 void
276 setCCRegOperand(const StaticInst *si, int idx, TheISA::CCReg val)
277 {
278 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
279 thread.setCCReg(reg_idx, val);
280 }
281
282 void
283 demapInstPage(Addr vaddr, uint64_t asn)
284 {
285 thread.getITBPtr()->demapPage(vaddr, asn);
286 }
287
288 void
289 demapDataPage(Addr vaddr, uint64_t asn)
290 {
291 thread.getDTBPtr()->demapPage(vaddr, asn);
292 }
293
294 /* ALPHA/POWER: Effective address storage */
|
298 void setEA(Addr &ea)
| 295 void setEA(Addr ea)
|
299 {
300 inst->ea = ea;
301 }
302
303 BaseCPU *getCpuPtr() { return &cpu; }
304
305 /* POWER: Effective address storage */
| 296 {
297 inst->ea = ea;
298 }
299
300 BaseCPU *getCpuPtr() { return &cpu; }
301
302 /* POWER: Effective address storage */
|
306 Addr getEA()
| 303 Addr getEA() const
|
307 {
308 return inst->ea;
309 }
310
311 /* MIPS: other thread register reading/writing */
312 uint64_t
| 304 {
305 return inst->ea;
306 }
307
308 /* MIPS: other thread register reading/writing */
309 uint64_t
|
313 readRegOtherThread(unsigned idx, ThreadID tid = InvalidThreadID)
| 310 readRegOtherThread(int idx, ThreadID tid = InvalidThreadID)
|
314 {
315 SimpleThread *other_thread = (tid == InvalidThreadID
316 ? &thread : cpu.threads[tid]);
317
318 if (idx < TheISA::FP_Reg_Base) { /* Integer */
319 return other_thread->readIntReg(idx);
320 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
321 return other_thread->readFloatRegBits(idx
322 - TheISA::FP_Reg_Base);
323 } else { /* Misc */
324 return other_thread->readMiscReg(idx
325 - TheISA::Misc_Reg_Base);
326 }
327 }
328
329 void
| 311 {
312 SimpleThread *other_thread = (tid == InvalidThreadID
313 ? &thread : cpu.threads[tid]);
314
315 if (idx < TheISA::FP_Reg_Base) { /* Integer */
316 return other_thread->readIntReg(idx);
317 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
318 return other_thread->readFloatRegBits(idx
319 - TheISA::FP_Reg_Base);
320 } else { /* Misc */
321 return other_thread->readMiscReg(idx
322 - TheISA::Misc_Reg_Base);
323 }
324 }
325
326 void
|
330 setRegOtherThread(unsigned idx, const TheISA::MiscReg &val,
| 327 setRegOtherThread(int idx, const TheISA::MiscReg &val,
|
331 ThreadID tid = InvalidThreadID)
332 {
333 SimpleThread *other_thread = (tid == InvalidThreadID
334 ? &thread : cpu.threads[tid]);
335
336 if (idx < TheISA::FP_Reg_Base) { /* Integer */
337 return other_thread->setIntReg(idx, val);
338 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
339 return other_thread->setFloatRegBits(idx
340 - TheISA::FP_Reg_Base, val);
341 } else { /* Misc */
342 return other_thread->setMiscReg(idx
343 - TheISA::Misc_Reg_Base, val);
344 }
345 }
346};
347
348}
349
350#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
| 328 ThreadID tid = InvalidThreadID)
329 {
330 SimpleThread *other_thread = (tid == InvalidThreadID
331 ? &thread : cpu.threads[tid]);
332
333 if (idx < TheISA::FP_Reg_Base) { /* Integer */
334 return other_thread->setIntReg(idx, val);
335 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
336 return other_thread->setFloatRegBits(idx
337 - TheISA::FP_Reg_Base, val);
338 } else { /* Misc */
339 return other_thread->setMiscReg(idx
340 - TheISA::Misc_Reg_Base, val);
341 }
342 }
343};
344
345}
346
347#endif /* __CPU_MINOR_EXEC_CONTEXT_HH__ */
|