1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 39 unchanged lines hidden (view full) ---

48 * @file
49 *
50 * ExecContext bears the exec_context interface for Minor.
51 */
52
53#ifndef __CPU_MINOR_EXEC_CONTEXT_HH__
54#define __CPU_MINOR_EXEC_CONTEXT_HH__
55
56#include "cpu/minor/execute.hh"
57#include "cpu/minor/pipeline.hh"
58#include "cpu/base.hh"
59#include "cpu/simple_thread.hh"
60#include "debug/MinorExecute.hh"
61
62namespace Minor
63{
64
65/* Forward declaration of Execute */
66class Execute;
67
68/** ExecContext bears the exec_context interface for Minor. This nicely
69 * separates that interface from other classes such as Pipeline, MinorCPU
70 * and DynMinorInst and makes it easier to see what state is accessed by it.
71 */
72class ExecContext
73{
74 public:
75 MinorCPU &cpu;
76
77 /** ThreadState object, provides all the architectural state. */
78 SimpleThread &thread;
79
80 /** The execute stage so we can peek at its contents. */

--- 33 unchanged lines hidden (view full) ---

114 writeMem(uint8_t *data, unsigned int size, Addr addr,
115 unsigned int flags, uint64_t *res)
116 {
117 execute.getLSQ().pushRequest(inst, false /* store */, data,
118 size, addr, flags, res);
119 return NoFault;
120 }
121
122 uint64_t
123 readIntRegOperand(const StaticInst *si, int idx)
124 {
125 return thread.readIntReg(si->srcRegIdx(idx));
126 }
127
128 TheISA::FloatReg
129 readFloatRegOperand(const StaticInst *si, int idx)
130 {

--- 4 unchanged lines hidden (view full) ---

135 TheISA::FloatRegBits
136 readFloatRegOperandBits(const StaticInst *si, int idx)
137 {
138 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
139 return thread.readFloatRegBits(reg_idx);
140 }
141
142 void
143 setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
144 {
145 thread.setIntReg(si->destRegIdx(idx), val);
146 }
147
148 void
149 setFloatRegOperand(const StaticInst *si, int idx,
150 TheISA::FloatReg val)
151 {

--- 17 unchanged lines hidden (view full) ---

169
170 void
171 setPredicate(bool val)
172 {
173 thread.setPredicate(val);
174 }
175
176 TheISA::PCState
177 pcState()
178 {
179 return thread.pcState();
180 }
181
182 void
183 pcState(const TheISA::PCState &val)
184 {
185 thread.pcState(val);

--- 59 unchanged lines hidden (view full) ---

245 panic("Syscall emulation isn't available in FS mode.\n");
246
247 thread.syscall(callnum);
248 }
249
250 ThreadContext *tcBase() { return thread.getTC(); }
251
252 /* @todo, should make stCondFailures persistent somewhere */
253 unsigned int readStCondFailures() { return 0; }
254 unsigned int
255 setStCondFailures(unsigned int st_cond_failures)
256 {
257 return 0;
258 }
259
260 int contextId() { return thread.contextId(); }
261 /* ISA-specific (or at least currently ISA singleton) functions */
262
263 /* X86: TLB twiddling */
264 void
265 demapPage(Addr vaddr, uint64_t asn)
266 {

--- 23 unchanged lines hidden (view full) ---

290
291 void
292 demapDataPage(Addr vaddr, uint64_t asn)
293 {
294 thread.getDTBPtr()->demapPage(vaddr, asn);
295 }
296
297 /* ALPHA/POWER: Effective address storage */
298 void setEA(Addr &ea)
299 {
300 inst->ea = ea;
301 }
302
303 BaseCPU *getCpuPtr() { return &cpu; }
304
305 /* POWER: Effective address storage */
306 Addr getEA()
307 {
308 return inst->ea;
309 }
310
311 /* MIPS: other thread register reading/writing */
312 uint64_t
313 readRegOtherThread(unsigned idx, ThreadID tid = InvalidThreadID)
314 {
315 SimpleThread *other_thread = (tid == InvalidThreadID
316 ? &thread : cpu.threads[tid]);
317
318 if (idx < TheISA::FP_Reg_Base) { /* Integer */
319 return other_thread->readIntReg(idx);
320 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */
321 return other_thread->readFloatRegBits(idx
322 - TheISA::FP_Reg_Base);
323 } else { /* Misc */
324 return other_thread->readMiscReg(idx
325 - TheISA::Misc_Reg_Base);
326 }
327 }
328
329 void
330 setRegOtherThread(unsigned idx, const TheISA::MiscReg &val,
331 ThreadID tid = InvalidThreadID)
332 {
333 SimpleThread *other_thread = (tid == InvalidThreadID
334 ? &thread : cpu.threads[tid]);
335
336 if (idx < TheISA::FP_Reg_Base) { /* Integer */
337 return other_thread->setIntReg(idx, val);
338 } else if (idx < TheISA::Misc_Reg_Base) { /* Float */

--- 12 unchanged lines hidden ---