dyn_inst.hh (12104:edd63f9c6184) | dyn_inst.hh (12420:f5c80f4ed41f) |
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1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 207 unchanged lines hidden (view full) --- 216 * to account for delay in absolute time */ 217 Cycles minimumCommitCycle; 218 219 /** Flat register indices so that, when clearing the scoreboard, we 220 * have the same register indices as when the instruction was marked 221 * up */ 222 RegId flatDestRegIdx[TheISA::MaxInstDestRegs]; 223 | 1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 207 unchanged lines hidden (view full) --- 216 * to account for delay in absolute time */ 217 Cycles minimumCommitCycle; 218 219 /** Flat register indices so that, when clearing the scoreboard, we 220 * have the same register indices as when the instruction was marked 221 * up */ 222 RegId flatDestRegIdx[TheISA::MaxInstDestRegs]; 223 |
224 /** Effective address as set by ExecContext::setEA */ 225 Addr ea; 226 | |
227 public: 228 MinorDynInst(InstId id_ = InstId(), Fault fault_ = NoFault) : 229 staticInst(NULL), id(id_), traceData(NULL), 230 pc(TheISA::PCState(0)), fault(fault_), 231 triedToPredict(false), predictedTaken(false), 232 fuIndex(0), inLSQ(false), inStoreBuffer(false), 233 canEarlyIssue(false), 234 instToWaitFor(0), extraCommitDelay(Cycles(0)), | 224 public: 225 MinorDynInst(InstId id_ = InstId(), Fault fault_ = NoFault) : 226 staticInst(NULL), id(id_), traceData(NULL), 227 pc(TheISA::PCState(0)), fault(fault_), 228 triedToPredict(false), predictedTaken(false), 229 fuIndex(0), inLSQ(false), inStoreBuffer(false), 230 canEarlyIssue(false), 231 instToWaitFor(0), extraCommitDelay(Cycles(0)), |
235 extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0)), 236 ea(0) | 232 extraCommitDelayExpr(NULL), minimumCommitCycle(Cycles(0)) |
237 { } 238 239 public: 240 /** The BubbleIF interface. */ 241 bool isBubble() const { return id.fetchSeqNum == 0; } 242 243 /** There is a single bubble inst */ 244 static MinorDynInstPtr bubble() { return bubbleInst; } --- 37 unchanged lines hidden --- | 233 { } 234 235 public: 236 /** The BubbleIF interface. */ 237 bool isBubble() const { return id.fetchSeqNum == 0; } 238 239 /** There is a single bubble inst */ 240 static MinorDynInstPtr bubble() { return bubbleInst; } --- 37 unchanged lines hidden --- |