dyn_inst.cc (12109:f29e9c5418aa) | dyn_inst.cc (12392:e0dbdf30a2a5) |
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1/* 2 * Copyright (c) 2013-2014, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 155 unchanged lines hidden (view full) --- 164 if (reg.isZeroReg()) { 165 os << 'z'; 166 } else { 167 os << 'r' << static_cast<unsigned int>(reg.index()); 168 } 169 break; 170 case CCRegClass: 171 os << 'c' << static_cast<unsigned int>(reg.index()); | 1/* 2 * Copyright (c) 2013-2014, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 155 unchanged lines hidden (view full) --- 164 if (reg.isZeroReg()) { 165 os << 'z'; 166 } else { 167 os << 'r' << static_cast<unsigned int>(reg.index()); 168 } 169 break; 170 case CCRegClass: 171 os << 'c' << static_cast<unsigned int>(reg.index()); |
172 break; |
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172 default: 173 panic("Unknown register class: %d", (int)reg.classValue()); 174 } 175} 176 177void 178MinorDynInst::minorTraceInst(const Named &named_object) const 179{ --- 62 unchanged lines hidden --- | 173 default: 174 panic("Unknown register class: %d", (int)reg.classValue()); 175 } 176} 177 178void 179MinorDynInst::minorTraceInst(const Named &named_object) const 180{ --- 62 unchanged lines hidden --- |